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A Scheduled Based Argo NI NoC Using GALS Architecture for MPSOC

https://doi.org/10.2139/ssrn.3887480
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-981-13-8942-9_37openalex-extracted
Design and Implementation of Argo NI-NoC Micro-architecture for MPSoC Using GALS Architecture
inferredcites →https://doi.org/10.1007/s11235-015-0075-9openalex-extracted
Proposing an optimal structure for the architecture of wireless networks on chip
inferredcites →https://doi.org/10.1016/j.heliyon.2020.e03183openalex-extracted
Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies
inferredcites →https://doi.org/10.1016/j.jpdc.2018.09.009openalex-extracted
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines
inferredcites →https://doi.org/10.1049/cje.2017.08.018openalex-extracted
A Reconfigurable Hardware Architecture for Packet Processing
inferredcites →https://doi.org/10.1049/iet-com.2019.1033openalex-extracted
Flow control and scheduling mechanism to improve network performance in wireless NoC
inferredcites →https://doi.org/10.1080/00051144.2019.1674511openalex-extracted
Congestion-aware wireless network-on-chip for high-speed communication
inferredcites →https://doi.org/10.1109/access.2018.2882941openalex-extracted
Contention & Energy-Aware Real-Time Task Mapping on NoC Based Heterogeneous MPSoCs
inferredcites →https://doi.org/10.1109/access.2019.2943922openalex-extracted
An Approximate Bufferless Network-on-Chip
inferredcites →https://doi.org/10.1109/access.2020.2982675openalex-extracted
Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
inferredcites →https://doi.org/10.1109/compcomm.2016.7925054openalex-extracted
Traffic Allocation: An efficient adaptive network-on-chip routing algorithm design
inferredcites →https://doi.org/10.1109/gcat47503.2019.8978403openalex-extracted
Network-On-Chip (NoC) - Routing Techniques: A Study and Analysis
inferredcites →https://doi.org/10.1109/iciase45644.2019.9074082openalex-extracted
Performance Analysis of Routing Algorithms in Mesh Based Network on Chip using Booksim Simulator
inferredcites →https://doi.org/10.1109/icnas.2019.8807815openalex-extracted
Mapping and scheduling techniques in NoC: A survey of the state of the art
inferredcites →https://doi.org/10.1109/islped.2019.8824912openalex-extracted
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs
inferredcites →https://doi.org/10.1109/isqed.2016.7479205openalex-extracted
Power efficient router architecture for wireless Network-on-Chip
inferredcites →https://doi.org/10.1109/mtv.2003.1250272openalex-extracted
A deterministic globally asynchronous locally synchronous microprocessor architecture
inferredcites →https://doi.org/10.1109/norchip.2014.7004742openalex-extracted
Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools
inferredcites →https://doi.org/10.1109/rtest49666.2020.9140136openalex-extracted
ANDRESTA: An Automated NoC-Based Design Flow for Real-Time Streaming Applications
inferredcites →https://doi.org/10.1109/tcad.2010.2086930openalex-extracted
A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel
inferredcites →https://doi.org/10.1109/tcad.2019.2907909openalex-extracted
Enhancing Network-on-Chip Performance by Reusing Trace Buffers
inferredcites →https://doi.org/10.1109/tvlsi.2015.2405614openalex-extracted
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
inferredcites →https://doi.org/10.1109/tvlsi.2019.2899575openalex-extracted
RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA
inferredcites →https://doi.org/10.1145/1669112.1669145openalex-extracted
Low-cost router microarchitecture for on-chip networks
inferredcites →https://doi.org/10.1145/3269983openalex-extracted
Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
inferredcites →https://doi.org/10.1145/3336121openalex-extracted
Energy-efficient Static Task Scheduling on VFI-based NoC-HMPSoCs for Intelligent Edge Devices in Cyber-physical Systems
inferredcites →https://doi.org/10.1155/2020/8823938openalex-extracted
Scalable THz Network-On-Chip Architecture for Multichip Systems
inferredcites →https://doi.org/10.13142/kt10005.05openalex-extracted
FPGA Implementation of IP Packet Header Parsing Hardware
inferredcites →https://doi.org/10.17577/ijertv9is070295openalex-extracted
NoC Linked List based Router for Packet Classification Application
inferredcites →https://doi.org/10.3390/jlpea7020008openalex-extracted
Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity
inferredcites →https://doi.org/10.3390/jlpea7020014openalex-extracted
Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer
inferredcites →https://doi.org/10.35940/ijrte.f2131.037619openalex-extracted
Network on Chip: A Survey on Router Design and Algorithms
inferredcites →https://doi.org/10.48550/arxiv.1809.07862openalex-extracted
A Traffic-Aware Medium Access Control Mechanism for Energy-Efficient Wireless Network-on-Chip Architectures

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inferred← citeshttps://doi.org/10.1109/discover55800.2022.9974626openalex-snapshot
The Design and Implementation of Synchronous and Asynchronous NoC Router
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