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Why Attackers Lose: Design and Security Analysis of Arbitrarily Large XOR Arbiter PUFs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/cpe.805openalex-snapshot
Identification and authentication of integrated circuits
inferredcites →https://doi.org/10.1007/978-1-4419-8080-9openalex-snapshot
Introduction to Hardware Security and Trust
inferredcites →https://doi.org/10.1007/978-3-319-22846-4_2openalex-snapshot
Why Attackers Win: On the Learnability of XOR Arbiter PUFs
inferredcites →https://doi.org/10.1007/978-3-319-29485-8_16openalex-snapshot
Towards a Unified Security Model for Physically Unclonable Functions
inferredcites →https://doi.org/10.1007/978-3-319-45572-3_8openalex-snapshot
An Arbiter PUF Secured by Remote Random Reconfigurations of an FPGA
inferredcites →https://doi.org/10.1007/978-3-642-10366-7_40openalex-snapshot
Memory Leakage-Resilient Encryption Based on Physically Unclonable Functions
inferredcites →https://doi.org/10.1007/978-3-642-14452-3_6openalex-snapshot
Memory Leakage-Resilient Encryption Based on Physically Unclonable Functions
inferredcites →https://doi.org/10.1007/978-3-642-21599-5_3openalex-snapshot
Side-Channel Analysis of PUFs and Fuzzy Extractors
inferredcites →https://doi.org/10.1007/978-3-662-44709-3_26openalex-snapshot
Efficient Power and Timing Side Channels for Physical Unclonable Functions
inferredcites →https://doi.org/10.1007/978-3-662-44709-3_27openalex-snapshot
Physical Characterization of Arbiter PUFs
inferredcites →https://doi.org/10.1007/978-3-662-48324-4_27openalex-snapshot
The Gap Between Promise and Reality: On the Insecurity of XOR Arbiter PUFs
inferredcites →https://doi.org/10.1007/978-3-662-53140-2_19openalex-snapshot
Strong Machine Learning Attack Against PUFs with No Mathematical Model
inferredcites →https://doi.org/10.1007/978-3-662-53140-2_8openalex-snapshot
No Place to Hide: Contactless Probing of Secret Data on FPGAs
inferredcites →https://doi.org/10.1007/s13389-016-0119-4openalex-snapshot
PAC learning of arbiter PUFs
inferredcites →https://doi.org/10.1090/s0002-9947-1941-0003498-3openalex-snapshot
The Accuracy of the Gaussian Approximation to the Sum of Independent Variates
inferredcites →https://doi.org/10.1109/ats.2016.21openalex-snapshot
Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm
inferredcites →https://doi.org/10.1109/csac.2002.1176287openalex-snapshot
Controlled physical random functions
inferredcites →https://doi.org/10.1109/fdtc.2015.19openalex-snapshot
Laser Fault Attack on Physically Unclonable Functions
inferredcites →https://doi.org/10.1109/hst.2013.6581558openalex-snapshot
Novel strong PUF based on nonlinearity of MOSFET subthreshold operation
inferredcites →https://doi.org/10.1109/hst.2013.6581579openalex-snapshot
Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise
inferredcites →https://doi.org/10.1109/hst.2014.6855565openalex-snapshot
On design of a highly secure PUF based on non-linear current mirrors
inferredcites →https://doi.org/10.1109/rfid.2008.4519377openalex-snapshot
Design and Implementation of PUF-Based "Unclonable" RFID ICs for Anti-Counterfeiting and Security Applications
inferredcites →https://doi.org/10.1109/sp.2011.10openalex-snapshot
A Formal Foundation for the Security Features of Physical Functions
inferredcites →https://doi.org/10.1109/sp.2015.12openalex-snapshot
Virtual Proofs of Reality and their Physical Implementation
inferredcites →https://doi.org/10.1109/tcsi.2013.2290845openalex-snapshot
Fault Injection Modeling Attacks on 65 nm Arbiter and RO Sum PUFs via Environmental Changes
inferredcites →https://doi.org/10.1109/test.2010.5699248openalex-snapshot
Rapid FPGA delay characterization using clock synthesis and sparse sampling
inferredcites →https://doi.org/10.1109/tifs.2013.2279798openalex-snapshot
PUF Modeling Attacks on Simulated and Silicon Data
inferredcites →https://doi.org/10.1109/tmscs.2016.2553027openalex-snapshot
A Lockdown Technique to Prevent Machine Learning on PUFs for Lightweight Authentication
inferredcites →https://doi.org/10.1109/tvlsi.2005.859470openalex-snapshot
Extracting secret keys from integrated circuits
inferredcites →https://doi.org/10.1109/wifs.2010.5711471openalex-snapshot
FPGA PUF using programmable delay lines
inferredcites →https://doi.org/10.1145/1278480.1278484openalex-snapshot
Physical unclonable functions for device authentication and secret key generation
inferredcites →https://doi.org/10.1145/1866307.1866335openalex-snapshot
Modeling attacks on physical unclonable functions
inferredcites →https://doi.org/10.1145/2072274.2072276openalex-snapshot
Semi-invasive EM attack on FPGA RO PUFs and countermeasures
inferredcites →https://doi.org/10.1145/2810103.2813723openalex-snapshot
Lattice Basis Reduction Attack against Physically Unclonable Functions
inferredcites →https://doi.org/10.1145/586131.586132openalex-snapshot
Silicon physical random functions
inferredcites →https://doi.org/10.1145/952532.952593openalex-snapshot
Delay-based circuit authentication and applications
inferredcites →https://doi.org/10.1145/952589.952593openalex-snapshot
Delay-based circuit authentication and applications
inferredcites →https://doi.org/10.5555/2755753.2755903openalex-snapshot
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics
inferredcites →https://doi.org/10.7873/date.2015.0522openalex-snapshot
A Novel Modeling Attack Resistant PUF Design based on Non-linear Voltage Transfer Characteristics
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103180openalex-snapshot
Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance
inferred← citeshttps://doi.org/10.1088/1742-6596/1729/1/012006openalex-snapshot
Experimental Examination of Component-Differentially-Challenged XOR PUF Circuits
inferred← citeshttps://doi.org/10.1109/access.2022.3228635openalex-snapshot
Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security
inferred← citeshttps://doi.org/10.1109/eurospw.2019.00036openalex-snapshot
CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction
inferred← citeshttps://doi.org/10.1109/ises50453.2020.00039openalex-snapshot
Lightweight and Attack-resilient PUF for Internet of Things
inferred← citeshttps://doi.org/10.3390/s24010093openalex-snapshot
A Response-Feedback-Based Strong PUF with Improved Strict Avalanche Criterion and Reliability
inferred← citeshttps://doi.org/10.46586/tches.v2019.i4.243-290openalex-snapshot
The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks
inferred← citeshttps://doi.org/10.46586/tches.v2020.i3.97-120openalex-snapshot
Splitting the Interpose PUF: A Novel Modeling Attack Strategy
inferred← citeshttps://doi.org/10.46586/tches.v2021.i2.357-389openalex-snapshot
Combining Optimization Objectives: New Modeling Attacks on Strong PUFs
inferred← citeshttps://doi.org/10.46586/tches.v2024.i1.501-526openalex-snapshot
CalyPSO: An Enhanced Search Optimization based Framework to Model Delay-based PUFs
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