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Towards Efficient and Automated Side Channel Evaluations at Design Time
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11894063_7openalex-snapshot
Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations
inferredcites →https://doi.org/10.1007/3-540-44709-1_21openalex-snapshot
Electromagnetic Analysis: Concrete Results
inferredcites →https://doi.org/10.1007/3-540-48059-5_15openalex-snapshot
DES and Differential Power Analysis The “Duplication” Method
inferredcites →https://doi.org/10.1007/3-540-48405-1_26openalex-snapshot
Towards Sound Approaches to Counteract Power-Analysis Attacks
inferredcites →https://doi.org/10.1007/3-540-68697-5_9openalex-snapshot
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
inferredcites →https://doi.org/10.1007/978-3-319-64647-3_1openalex-snapshot
Does Coupling Affect the Security of Masked Implementations?
inferredcites →https://doi.org/10.1007/978-3-319-71667-1_20openalex-snapshot
Several Masked Implementations of the Boyar-Peralta AES S-Box
inferredcites →https://doi.org/10.1007/978-3-319-89641-0_14openalex-snapshot
A First-Order SCA Resistant AES Without Fresh Randomness
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_2openalex-snapshot
Correlation Power Analysis with a Leakage Model
inferredcites →https://doi.org/10.1007/978-3-540-74735-2_29openalex-snapshot
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
inferredcites →https://doi.org/10.1007/978-3-540-85053-3_27openalex-snapshot
Mutual Information Analysis
inferredcites →https://doi.org/10.1007/978-3-642-00730-9_14openalex-snapshot
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
inferredcites →https://doi.org/10.1007/978-3-642-01001-9_26openalex-snapshot
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
inferredcites →https://doi.org/10.1007/978-3-642-01004-0_13openalex-snapshot
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology
inferredcites →https://doi.org/10.1007/978-3-642-04138-9_15openalex-snapshot
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
inferredcites →https://doi.org/10.1007/s00145-010-9085-7openalex-snapshot
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches
inferredcites →https://doi.org/10.1007/s00145-010-9086-6openalex-snapshot
Side-Channel Resistant Crypto for Less than 2,300 GE
inferredcites →https://doi.org/10.1007/s13389-014-0080-zopenalex-snapshot
Understanding the limitations and improving the relevance of SPICE simulations in side-channel security evaluations
inferredcites →https://doi.org/10.1016/j.vlsi.2009.01.001openalex-snapshot
Vulnerability modeling of cryptographic hardware to power analysis attacks
inferredcites →https://doi.org/10.1109/dac.2005.193806openalex-snapshot
Simulation models for side-channel information leaks
inferredcites →https://doi.org/10.1109/date.2004.1268856openalex-snapshot
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
inferredcites →https://doi.org/10.1109/date.2005.44openalex-snapshot
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
inferredcites →https://doi.org/10.1109/hst.2011.5955002openalex-snapshot
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation
inferredcites →https://doi.org/10.1109/iscas.2006.1693233openalex-snapshot
Side Channel Analysis Resistant Design Flow
inferredcites →https://doi.org/10.1109/siecpc.2011.5876976openalex-snapshot
CCS vs NLDM comparison based on a complete automated correlation flow between PrimeTime and HSPICE
inferredcites →https://doi.org/10.1109/tcad.2005.855939openalex-snapshot
A digital design flow for secure integrated circuits
inferredcites →https://doi.org/10.1145/1065579.1065640openalex-snapshot
Simulation models for side-channel information leaks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-34618-8_10openalex-snapshot
Location, Location, Location: Revisiting Modeling and Exploitation for Location-Based Side Channel Leakages
inferred← citeshttps://doi.org/10.1007/978-3-030-68773-1_13openalex-snapshot
Integrating Side Channel Security in the FPGA Hardware Design Flow
inferred← citeshttps://doi.org/10.1007/978-3-030-89915-8_6openalex-snapshot
Protecting Secure ICs Against Side-Channel Attacks by Identifying and Quantifying Potential EM and Leakage Hotspots at Simulation Stage
inferred← citeshttps://doi.org/10.1007/978-3-030-99277-4_5openalex-snapshot
A Low-Randomness Second-Order Masked AES
inferred← citeshttps://doi.org/10.1007/978-3-031-26896-0_6openalex-snapshot
CAD for Power Side-Channel Detection
inferred← citeshttps://doi.org/10.1007/s11227-021-03927-wopenalex-snapshot
Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247834openalex-snapshot
On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00065openalex-snapshot
Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities
inferred← citeshttps://doi.org/10.1109/ets69887.2026.11591631openalex-snapshot
Bridging the Speed-Accuracy Gap: Layout-Aware Pre-Silicon Side-Channel Analysis
inferred← citeshttps://doi.org/10.1109/ises50453.2020.00038openalex-snapshot
Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis
inferred← citeshttps://doi.org/10.1109/lascas56464.2023.10108340openalex-snapshot
Security Implications of Decoupling Capacitors on Leakage Reduction in Hardware Masking
inferred← citeshttps://doi.org/10.1109/paine54418.2021.9707701openalex-snapshot
OPAL: On-the-go Physical Attack Lab to Evaluate Power Side-channel Vulnerabilities on FPGAs
inferred← citeshttps://doi.org/10.1109/tc.2023.3333164openalex-snapshot
VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection
inferred← citeshttps://doi.org/10.1109/tvlsi.2022.3175067openalex-snapshot
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level
inferred← citeshttps://doi.org/10.1145/3526241.3530337openalex-snapshot
Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment
inferred← citeshttps://doi.org/10.1145/3721294openalex-snapshot
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs
inferred← citeshttps://doi.org/10.1145/3768154openalex-snapshot
Boosting Cryptographic ICs’ Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116468openalex-snapshot
Sweeping for Leakage in Masked Circuit Layouts
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774531openalex-snapshot
A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time
inferred← citeshttps://doi.org/10.3390/info15080488openalex-snapshot
A Methodology to Distribute On-Chip Voltage Regulators to Improve the Security of Hardware Masking
inferred← citeshttps://doi.org/10.3390/s22187028openalex-snapshot
Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking
inferred← citeshttps://doi.org/10.46586/tches.v2019.i3.119-147openalex-snapshot
Consolidating Security Notions in Hardware Masking
inferred← citeshttps://doi.org/10.46586/tches.v2020.i2.73-98openalex-snapshot
FENL: an ISE to mitigate analogue micro-architectural leakage
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