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3D NAND Flash Based on Planar Cells
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/aspdac.2017.7858385openalex-snapshot
Temperature-aware data allocation strategy for 3D charge-trap flash memory
inferredcites →https://doi.org/10.1109/iedm.1987.191485openalex-snapshot
New ultra high density EPROM and flash EEPROM with NAND structure cell
inferredcites →https://doi.org/10.1109/iedm.2006.346822openalex-snapshot
Reliability Model of Bandgap Engineered SONOS (BE-SONOS)
inferredcites →https://doi.org/10.1109/iedm.2007.4418970openalex-snapshot
Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory
inferredcites →https://doi.org/10.1109/iedm.2009.5424231openalex-snapshot
Reliability of barrier engineered charge trapping devices for sub-30nm NAND flash
inferredcites →https://doi.org/10.1109/iedm.2010.5703447openalex-snapshot
Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application
inferredcites →https://doi.org/10.1109/iedm.2012.6478963openalex-snapshot
A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts
inferredcites →https://doi.org/10.1109/iedm.2012.6479111openalex-snapshot
Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device
inferredcites →https://doi.org/10.1109/iedm.2014.7047085openalex-snapshot
A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials
inferredcites →https://doi.org/10.1109/iedm.2015.7409617openalex-snapshot
A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity
inferredcites →https://doi.org/10.1109/iedm.2015.7409618openalex-snapshot
A floating gate based 3D NAND technology with CMOS under array
inferredcites →https://doi.org/10.1109/imw.2009.5090581openalex-snapshot
BiCS Flash as a Future 3D Non-Volatile Memory Technology for Ultra High Density Storage Devices
inferredcites →https://doi.org/10.1109/imw.2010.5488390openalex-snapshot
A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability
inferredcites →https://doi.org/10.1109/imw.2010.5488392openalex-snapshot
The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the Extended Sidewall Control Gate (ESCG)
inferredcites →https://doi.org/10.1109/imw.2015.7150273openalex-snapshot
A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance
inferredcites →https://doi.org/10.1109/imw.2016.7493562openalex-snapshot
A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering
inferredcites →https://doi.org/10.1109/imw.2016.7495265openalex-snapshot
Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture
inferredcites →https://doi.org/10.1109/isscc.2014.6757458openalex-snapshot
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming
inferredcites →https://doi.org/10.1109/isscc.2016.7417947openalex-snapshot
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory
inferredcites →https://doi.org/10.1109/jssc.2015.2413841openalex-snapshot
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations
inferredcites →https://doi.org/10.1109/led.2007.895421openalex-snapshot
A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory
inferredcites →https://doi.org/10.1109/led.2013.2274472openalex-snapshot
Highly Scalable Horizontal Channel 3-D NAND Memory Excellent in Compatibility With Conventional Fabrication Technology
inferredcites →https://doi.org/10.1109/led.2015.2399107openalex-snapshot
A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND
inferredcites →https://doi.org/10.1109/nvmts.2014.7060840openalex-snapshot
A world's first product of three-dimensional vertical NAND Flash memory and beyond
inferredcites →https://doi.org/10.1109/tvlsi.2013.2288687openalex-snapshot
A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory
inferredcites →https://doi.org/10.1109/vlsit.2007.4339708openalex-snapshot
Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory
inferredcites →https://doi.org/10.1109/vlsit.2010.5556199openalex-snapshot
A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device
inferredcites →https://doi.org/10.1109/vlsit.2012.6242440openalex-snapshot
A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory
inferredcites →https://doi.org/10.1109/vlsit.2015.7223669openalex-snapshot
A novel dichotomic programming algorithm applied to 3D NAND flash
inferredcites →https://doi.org/10.1109/vtsa.2007.378899openalex-snapshot
A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory
inferredcites →https://doi.org/10.1109/vtsa.2010.5488917openalex-snapshot
Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9783527847419.ch3openalex-snapshot
Reliability Challenges of NAND Flash Memory in Harsh Environments
inferred← citeshttps://doi.org/10.1002/aelm.202200998openalex-snapshot
Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading
inferred← citeshttps://doi.org/10.1007/s40042-022-00456-4openalex-snapshot
Triple boron doped silicon for selective epitaxial growth of 3D NAND flash memory
inferred← citeshttps://doi.org/10.1016/j.apsusc.2021.149481openalex-snapshot
Density functional theory study on the modification of silicon nitride surface by fluorine-containing molecules
inferred← citeshttps://doi.org/10.1021/acsaelm.6c01476openalex-snapshot
Deep-Level Trap Engineering in Sn-Doped β-Ga2O3 MISFETs for Optoelectronic Memory and Reconfigurable Logic Application
inferred← citeshttps://doi.org/10.1088/1361-6633/ab8f86openalex-snapshot
Memory technology—a primer for material scientists
inferred← citeshttps://doi.org/10.1109/access.2020.3012012openalex-snapshot
An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND
inferred← citeshttps://doi.org/10.1109/irps45951.2020.9128219openalex-snapshot
Radiation Tolerance of 3-D NAND Flash Based Neuromorphic Computing System
inferred← citeshttps://doi.org/10.1109/tcad.2023.3238845openalex-snapshot
LDPC Level Prediction Toward Read Performance of High-Density Flash Memories
inferred← citeshttps://doi.org/10.1109/tns.2020.3014261openalex-snapshot
Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation
inferred← citeshttps://doi.org/10.1117/12.3034398openalex-snapshot
Ultra high speed integrated millimeter wave photonic vertical NAND FLASH with multiple VCSELs
inferred← citeshttps://doi.org/10.1117/12.3034437openalex-snapshot
Integrated ultra-high-speed vertical NAND FLASH VCSEL and high-power CMOS VCSEL for advanced silicon photonics applications
inferred← citeshttps://doi.org/10.1117/12.3034629openalex-snapshot
Integrated multiplexed sub-1nm optoelectronic millimeter wave CMOS technology for embedded non-volatile data storage, photonic IC with microwave VCSEL arrays, and high voltage, high cut-off frequency nano-wireless RF ASICs
inferred← citeshttps://doi.org/10.1145/3585075openalex-snapshot
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics
inferred← citeshttps://doi.org/10.1557/s43579-025-00708-xopenalex-snapshot
Ultra-high speed photonic vertical NAND FLASH and novel integrated vertical cavity surface emitting lasers (VCSELs)
inferred← citeshttps://doi.org/10.3390/mi14112007openalex-snapshot
Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory
inferred← citeshttps://doi.org/10.3390/s24103089openalex-snapshot
Enhancing Si3N4 Selectivity over SiO2 in Low-RF Power NF3–O2 Reactive Ion Etching: The Effect of NO Surface Reaction
inferred← citeshttps://doi.org/10.35848/1347-4065/ae5977openalex-snapshot
Silicon nitride chamber dry cleaning with carbonyl fluoride and nitrous oxide additives
inferred← citeshttps://doi.org/10.4028/www.scientific.net/ssp.282.3openalex-snapshot
Industry Context for Semiconductor Wet Etch and Surface Preparation
inferred← citeshttps://doi.org/10.48550/arxiv.1905.04767openalex-snapshot
Moving Processing to Data: On the Influence of Processing in Memory on Data Management
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