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Optimising Hardware Accelerated Neural Networks with Quantisation and a Knowledge Distillation Evolutionary Algorithm
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-030-01216-8_12openalex-snapshot
Exploring the Limits of Weakly Supervised Pretraining
inferredcites →https://doi.org/10.1007/978-3-030-01252-6_32openalex-snapshot
DPP-Net: Device-Aware Progressive Search for Pareto-Optimal Neural Architectures
inferredcites →https://doi.org/10.1007/978-3-030-64437-6_4openalex-snapshot
Neural Networks, Secure by Construction
inferredcites →https://doi.org/10.1007/978-3-319-63387-9_5openalex-snapshot
Reluplex: An Efficient SMT Solver for Verifying Deep Neural Networks
inferredcites →https://doi.org/10.1007/978-3-319-78890-6_3openalex-snapshot
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic
inferredcites →https://doi.org/10.1007/s11633-016-1024-0openalex-snapshot
Review of some advances and applications in real-time high-speed vision: Our views and experiences
inferredcites →https://doi.org/10.1016/j.neucom.2017.09.046openalex-snapshot
FP-BNN: Binarized neural network on FPGA
inferredcites →https://doi.org/10.1109/4235.996017openalex-snapshot
A fast and elitist multiobjective genetic algorithm: NSGA-II
inferredcites →https://doi.org/10.1109/5.726791openalex-snapshot
Gradient-based learning applied to document recognition
inferredcites →https://doi.org/10.1109/cvpr.2017.415openalex-snapshot
PolyNet: A Pursuit of Structural Diversity in Very Deep Networks
inferredcites →https://doi.org/10.1109/cvpr.2018.00291openalex-snapshot
CondenseNet: An Efficient DenseNet Using Learned Group Convolutions
inferredcites →https://doi.org/10.1109/fpl.2014.6927483openalex-snapshot
Trends of CPU, GPU and FPGA for high-performance computing
inferredcites →https://doi.org/10.1109/fpl.2018.00024openalex-snapshot
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs
inferredcites →https://doi.org/10.1109/fpl.2018.00035openalex-snapshot
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA
inferredcites →https://doi.org/10.1109/icassp.2016.7471828openalex-snapshot
FPGA based implementation of deep neural networks using on-chip memory only
inferredcites →https://doi.org/10.1109/icfpt47387.2019.00014openalex-snapshot
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs
inferredcites →https://doi.org/10.1109/icip.2018.8451576openalex-snapshot
Flexible Network Binarization with Layer-Wise Priority
inferredcites →https://doi.org/10.1109/iiswc47752.2019.9042000openalex-snapshot
Performance Aware Convolutional Neural Network Channel Pruning for Embedded GPUs
inferredcites →https://doi.org/10.1109/ijcnn48605.2020.9207596openalex-snapshot
Relative Robustness of Quantized Neural Networks Against Adversarial Attacks
inferredcites →https://doi.org/10.1109/iv47402.2020.9304548openalex-snapshot
Towards Robust Direct Perception Networks for Automated Driving
inferredcites →https://doi.org/10.1109/tcsvt.2020.3020569openalex-snapshot
Layer-Specific Optimization for Mixed Data Flow With Mixed Precision in FPGA Design for CNN-Based Object Detectors
inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3065386openalex-snapshot
ImageNet classification with deep convolutional neural networks
inferredcites →https://doi.org/10.1145/3309551openalex-snapshot
Deep Neural Network Approximation for Custom Hardware
inferredcites →https://doi.org/10.1162/106365602320169811openalex-snapshot
Evolving Neural Networks through Augmenting Topologies
inferredcites →https://doi.org/10.1561/2400000035openalex-snapshot
Algorithms for Verifying Deep Neural Networks
inferredcites →https://doi.org/10.1609/aaai.v31i1.11231openalex-snapshot
Inception-v4, Inception-ResNet and the Impact of Residual Connections on Learning
inferredcites →https://doi.org/10.17863/cam.46508openalex-snapshot
Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs
inferredcites →https://doi.org/10.48550/arxiv.1503.02531openalex-snapshot
Distilling the Knowledge in a Neural Network
inferredcites →https://doi.org/10.48550/arxiv.1609.07061openalex-snapshot
Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations
inferredcites →https://doi.org/10.48550/arxiv.1802.05668openalex-snapshot
Model compression via distillation and quantization
inferredcites →https://doi.org/10.48550/arxiv.1810.10460openalex-snapshot
Distilling with Performance Enhanced Students
inferredcites →https://doi.org/10.48550/arxiv.1905.11946openalex-snapshot
EfficientNet: Rethinking Model Scaling for Convolutional Neural Networks
inferredcites →https://doi.org/10.48550/arxiv.1910.12232openalex-snapshot
Neural Network Distiller: A Python Package For DNN Compression Research
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-89698-0_31openalex-snapshot
A Time-Space Exchange Autoencoder for Image Super-Resolution
inferred← citeshttps://doi.org/10.1007/978-3-031-42921-7_20openalex-snapshot
Energy Efficient DNN Compaction for Edge Deployment
inferred← citeshttps://doi.org/10.1007/978-981-99-3814-8_12openalex-snapshot
Hardware-Aware Evolutionary Approaches to Deep Neural Networks
inferred← citeshttps://doi.org/10.1007/s11227-025-07380-xopenalex-snapshot
HW-SW co-design of image classification accelerator on FPGA
inferred← citeshttps://doi.org/10.1007/s11265-023-01883-7openalex-snapshot
FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/aero55745.2023.10115598openalex-snapshot
Self-supervised Distillation for Computer Vision Onboard Planetary Robots
inferred← citeshttps://doi.org/10.1109/asyu58738.2023.10296630openalex-snapshot
Implementation and Optimization of LeNet-5 Model for Handwritten Digits Recognition on FPGAs using Brevitas and FINN
inferred← citeshttps://doi.org/10.1109/dasc/picom/cbdcom/cy55231.2022.9927825openalex-snapshot
Design-Space Exploration of Quantized Transposed Convolutional Neural Networks for FPGA-based Systems-on-Chip
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00043openalex-snapshot
ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
inferred← citeshttps://doi.org/10.1109/ijcnn55064.2022.9892671openalex-snapshot
Accuracy Evaluation of Transposed Convolution-Based Quantized Neural Networks
inferred← citeshttps://doi.org/10.1109/mdat.2022.3161126openalex-snapshot
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms
inferred← citeshttps://doi.org/10.1137/1.9781611977653.ch63openalex-snapshot
Adaptive Precision Training (AdaPT): A dynamic quantized training approach for DNNs
inferred← citeshttps://doi.org/10.1145/3603704openalex-snapshot
Survey on Evolutionary Deep Learning: Principles, Algorithms, Applications, and Open Issues
inferred← citeshttps://doi.org/10.2514/1.a35767openalex-snapshot
CLOVER: Contrastive Learning for Onboard Vision-Enabled Robotics
inferred← citeshttps://doi.org/10.3390/electronics11060937openalex-snapshot
IE-Net: Information-Enhanced Binary Neural Networks for Accurate Classification
inferred← citeshttps://doi.org/10.3390/electronics11071066openalex-snapshot
A Novel Deep Learning Model Compression Algorithm
inferred← citeshttps://doi.org/10.3390/electronics14091704openalex-snapshot
FPGA-Based Low-Power High-Performance CNN Accelerator Integrating DIST for Rice Leaf Disease Classification
inferred← citeshttps://doi.org/10.3390/s24175813openalex-snapshot
A Comprehensive Review of Hardware Acceleration Techniques and Convolutional Neural Networks for EEG Signals
inferred← citeshttps://doi.org/10.62486/latia2025329openalex-snapshot
AI in Dissertation Examination: Opportunities for Undergraduates and Postgraduates in Zambia, Rwanda, and Kenya
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