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Bubble-Proof Algorithm for Wave Union TDCs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1063/1.4997244openalex-snapshot
Picosecond-precision multichannel autonomous time and frequency counter
inferredcites →https://doi.org/10.1088/0026-1394/41/1/004openalex-snapshot
Review of methods for time interval measurements with picosecond resolution
inferredcites →https://doi.org/10.1088/1748-0221/13/05/p05012openalex-snapshot
A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA
inferredcites →https://doi.org/10.1088/1748-0221/16/01/p01012openalex-snapshot
A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs
inferredcites →https://doi.org/10.1088/1748-0221/8/12/c12043openalex-snapshot
TRB3: a 264 channel high precision TDC platform and its applications
inferredcites →https://doi.org/10.1109/access.2021.3088448openalex-snapshot
Time-to-Digital Converter IP-Core for FPGA at State of the Art
inferredcites →https://doi.org/10.1109/ats.2006.260991openalex-snapshot
Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator
inferredcites →https://doi.org/10.1109/ebccsp51266.2020.9291360openalex-snapshot
Multi-channel high-linearity time-to-digital converters in 20 nm and 28 nm FPGAs for LiDAR applications
inferredcites →https://doi.org/10.1109/ebccsp51266.2020.9291363openalex-snapshot
Multisampling wave union time-to-digital converter
inferredcites →https://doi.org/10.1109/ebccsp53293.2021.9502360openalex-snapshot
A brief review of wave union TDCs
inferredcites →https://doi.org/10.1109/nssmic.2008.4775079openalex-snapshot
The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay
inferredcites →https://doi.org/10.1109/tencon.2004.1414916openalex-snapshot
A multiplexer based decoder for flash analog-to-digital converters
inferredcites →https://doi.org/10.1109/tie.2018.2842787openalex-snapshot
Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs
inferredcites →https://doi.org/10.1109/tie.2021.3053905openalex-snapshot
Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods
inferredcites →https://doi.org/10.1109/tim.2016.2555218openalex-snapshot
High-Precision Time Digitizer Based on Multiedge Coding in Independent Coding Lines
inferredcites →https://doi.org/10.1109/tns.2010.2045901openalex-snapshot
Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs
inferredcites →https://doi.org/10.1109/tns.2011.2141684openalex-snapshot
A High-Resolution ( ${< 10}~{\rm ps}$ RMS) 48-Channel Time-to-Digital Converter (TDC) Implemented in a Field Programmable Gate Array (FPGA)
inferredcites →https://doi.org/10.1109/tns.2013.2265555openalex-snapshot
A Stepped-Up Tree Encoder for the 10-ps Wave Union TDC
inferredcites →https://doi.org/10.1109/tns.2015.2421319openalex-snapshot
A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA
inferredcites →https://doi.org/10.1109/tns.2017.2746626openalex-snapshot
A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA
inferredcites →https://doi.org/10.1109/tns.2019.2938571openalex-snapshot
A 3.0-ps rms Precision 277-MSamples/s Throughput Time-to-Digital Converter Using Multi-Edge Encoding Scheme in a Kintex-7 FPGA
inferredcites →https://doi.org/10.1109/tns.2021.3085564openalex-snapshot
A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade
inferredcites →https://doi.org/10.24425/mms.2021.137697openalex-snapshot
Methods of precise determining the transfer function of picosecond time-to-digital converters
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-981-99-1916-1_17openalex-snapshot
Trimmed-TDL-Based Time-to-Digital Converter for Time-of-Flight Applications Implemented on Cyclone V FPGA
inferred← citeshttps://doi.org/10.1016/j.measurement.2022.112258openalex-snapshot
High-resolution time-to-digital converters (TDCs) with a bidirectional encoder
inferred← citeshttps://doi.org/10.1016/j.measurement.2023.112510openalex-snapshot
Subpicosecond resolution time interval counter with multisampling wave union type B TDCs in 28 nm FPGA device
inferred← citeshttps://doi.org/10.1016/j.measurement.2024.115313openalex-snapshot
Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters
inferred← citeshttps://doi.org/10.1016/j.measurement.2024.115523openalex-snapshot
Hybrid ALM-DSP TDC in Intel Arria 10 FPGA
inferred← citeshttps://doi.org/10.1016/j.nima.2025.170201openalex-snapshot
Single measurement wave union time-to-digital converter with a subsampling-scheme-based codification
inferred← citeshttps://doi.org/10.1109/mim.2023.10217031openalex-snapshot
Potential Use of State-of-the-Art TDCs for Particle Identification in Particle Physics Experiments
inferred← citeshttps://doi.org/10.1109/tim.2023.3267566openalex-snapshot
Trimmed-TDL-Based TDC Architecture for Time-of-Flight Measurements Tested on a Cyclone V FPGA
inferred← citeshttps://doi.org/10.1109/tim.2023.3277958openalex-snapshot
A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock
inferred← citeshttps://doi.org/10.1109/tns.2024.3400298openalex-snapshot
Design and Test of a Time-to-Digital Converter ASIC Based on a Differential Delay Line
inferred← citeshttps://doi.org/10.1109/tns.2026.3696036openalex-snapshot
An FPGA-Based Hybrid Wave Union Time-to-Digital Converter With Iterative Z-Type Code Calibration Algorithm
inferred← citeshttps://doi.org/10.1109/trustcom60117.2023.00259openalex-snapshot
A Near-Field EM Sensor Implemented in FPGA Configurable Fabric
inferred← citeshttps://doi.org/10.17323/10.17323/2713-2749.2023.2.78.121openalex-snapshot
Balancing Cyber-security and Privacy: Legal and Ethical Considerations in the Digital Age
inferred← citeshttps://doi.org/10.3390/electronics13122359openalex-snapshot
High-Performance Wave Union Time-to-Digital Converter Implementation Based on Routing Path Delays of FPGA
inferred← citeshttps://doi.org/10.3390/electronics13244888openalex-snapshot
Optimal Implementation of Tapped Delay Line Time-to-Digital Converters in 20 nm Xilinx UltraScale FPGAs
inferred← citeshttps://doi.org/10.3390/s23146621openalex-snapshot
A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method
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