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A Survey of Network-Based Hardware Accelerators
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/cpe.6055openalex-snapshot
A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip
inferredcites →https://doi.org/10.1007/978-1-4614-1791-0openalex-snapshot
High-Performance Computing Using FPGAs
inferredcites →https://doi.org/10.1007/978-3-030-20721-2openalex-snapshot
FPGA-BASED Hardware Accelerators
inferredcites →https://doi.org/10.1007/s00521-018-3761-1openalex-snapshot
A survey of FPGA-based accelerators for convolutional neural networks
inferredcites →https://doi.org/10.1007/s00607-013-0360-yopenalex-snapshot
Design and implementation of counting networks
inferredcites →https://doi.org/10.1007/s11432-016-5588-7openalex-snapshot
The Sunway TaihuLight supercomputer: system and applications
inferredcites →https://doi.org/10.1007/s11740-020-00964-xopenalex-snapshot
Data acquisition and control at the edge: a hardware/software-reconfigurable approach
inferredcites →https://doi.org/10.1016/j.micpro.2014.03.003openalex-snapshot
High-performance implementation of regular and easily scalable sorting networks on an FPGA
inferredcites →https://doi.org/10.1016/j.micpro.2019.05.012openalex-snapshot
Constraint programming in embedded systems design: Considered helpful
inferredcites →https://doi.org/10.1038/s41928-018-0057-5openalex-snapshot
High-performance parallel computing for next-generation holographic imaging
inferredcites →https://doi.org/10.1049/el:20070141openalex-snapshot
Efficient Hamming weight comparators of binary vectors
inferredcites →https://doi.org/10.1109/actea.2019.8851099openalex-snapshot
Hardware Architecture For A Shift-Based Parallel Odd-Even Transposition Sorting Network
inferredcites →https://doi.org/10.1109/colcomcon.2019.8809112openalex-snapshot
Implementation of a parameterizable sorting network for spatial modulation detection on FPGA
inferredcites →https://doi.org/10.1109/ipdpsw.2014.36openalex-snapshot
A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders
inferredcites →https://doi.org/10.1109/iscas.2004.1329339openalex-snapshot
Compact Hamming-Comparator-based rank order filter for digital VLSI and FPGA implementations
inferredcites →https://doi.org/10.1109/jproc.2018.2802438openalex-snapshot
Onboard Processing With Hybrid and Reconfigurable Computing on Small Satellites
inferredcites →https://doi.org/10.1109/mcas.2021.3071609openalex-snapshot
A Survey of FPGA-Based Robotic Computing
inferredcites →https://doi.org/10.1109/reconfig.2015.7393322openalex-snapshot
A hybrid design for high performance large-scale sorting on FPGA
inferredcites →https://doi.org/10.1109/tc.2012.108openalex-snapshot
Modular Design of High-Throughput, Low-Latency Sorting Units
inferredcites →https://doi.org/10.1109/tcsi.2008.924892openalex-snapshot
Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation
inferredcites →https://doi.org/10.1109/tcsii.2008.2010176openalex-snapshot
Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters
inferredcites →https://doi.org/10.1109/tip.2014.2311656openalex-snapshot
A Distributed Canny Edge Detector: Algorithm and FPGA Implementation
inferredcites →https://doi.org/10.1109/tpds.2021.3104257openalex-snapshot
EXA2PRO: A Framework for High Development Productivity on Heterogeneous Computing Systems
inferredcites →https://doi.org/10.1109/tpds.2021.3124125openalex-snapshot
FARNN: FPGA-GPU Hybrid Acceleration Platform for Recurrent Neural Networks
inferredcites →https://doi.org/10.1109/tvlsi.2018.2822300openalex-snapshot
Low-Cost Sorting Network Circuits Using Unary Processing
inferredcites →https://doi.org/10.1109/tvlsi.2019.2905242openalex-snapshot
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
inferredcites →https://doi.org/10.1109/tvlsi.2019.2912554openalex-snapshot
RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm
inferredcites →https://doi.org/10.1145/2228360.2228588openalex-snapshot
Computer generation of streaming sorting networks
inferredcites →https://doi.org/10.1145/2684746.2689068openalex-snapshot
Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA
inferredcites →https://doi.org/10.1145/3079758openalex-snapshot
Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1155/2016/8972065openalex-snapshot
On-Chip Reconfigurable Hardware Accelerators for Popcount Computations
inferredcites →https://doi.org/10.1587/transinf.2016edp7383openalex-snapshot
A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism
inferredcites →https://doi.org/10.23919/fpl.2017.8056756openalex-snapshot
Evaluating high-level design strategies on FPGAs for high-performance computing
inferredcites →https://doi.org/10.3176/proc.2017.3.07openalex-snapshot
Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems; pp. 323–335
inferredcites →https://doi.org/10.3390/a13020047openalex-snapshot
Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs
inferredcites →https://doi.org/10.3390/electronics10080895openalex-snapshot
Embedded Intelligence on FPGA: Survey, Applications and Challenges
inferredcites →https://doi.org/10.3390/en11092394openalex-snapshot
FPGA-Based Implementation of MMC Control Based on Sorting Networks
inferredcites →https://doi.org/10.3390/jlpea11020020openalex-snapshot
Accelerating Population Count with a Hardware Co-Processor for MicroBlaze
inferredcites →https://doi.org/10.3390/s18061877openalex-snapshot
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework
inferredcites →https://doi.org/10.3929/ethz-a-006153077openalex-snapshot
Data Stream Processing on Embedded Devices
inferredcites →https://doi.org/10.4316/aece.2013.04008openalex-snapshot
Fast Regular Circuits for Network-based Parallel Data Processing
inferredcites →https://doi.org/10.6180/jase.202202_25(1).0001openalex-snapshot
Real-Time High Definition License Plate Localization and Recognition Accelerator for IoT Endpoint System on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1051/epjconf/202429502006openalex-snapshot
Cluster reconstruction in the HGCAL at the Level 1 trigger
inferred← citeshttps://doi.org/10.1109/access.2024.3357352openalex-snapshot
Design Space Exploration of HW Accelerators and Network Infrastructure for FPGA-Based MPSoC
inferred← citeshttps://doi.org/10.1109/icit56493.2022.9989124openalex-snapshot
Hardware Accelerators And Accelerators For Machine Learning
inferred← citeshttps://doi.org/10.1109/isvlsi65124.2025.11130285openalex-snapshot
Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA
inferred← citeshttps://doi.org/10.1145/3641584.3641723openalex-snapshot
A Multi-Precision Floating-Point Multiplier Structure Applied to FPGA Embedded DSP
inferred← citeshttps://doi.org/10.1145/3734797openalex-snapshot
Sorting it out in Hardware: A State-of-the-Art Survey
inferred← citeshttps://doi.org/10.17485/ijst/v15i45.1384openalex-snapshot
FPGA Design for Low Delay Comparison-free, Odd-even Merge Sorter
inferred← citeshttps://doi.org/10.3233/atde230112openalex-snapshot
A FPGA Embedded DSP Supporting Parallel Multiple Low Bit-Width Multiply-Accumulate Operations
inferred← citeshttps://doi.org/10.3390/app12168065openalex-snapshot
Improving Hardware in LUT-Based Mealy FSMs
inferred← citeshttps://doi.org/10.3390/app131810200openalex-snapshot
Improving Characteristics of FPGA-Based FSMs Representing Sequential Blocks of Cyber-Physical Systems
inferred← citeshttps://doi.org/10.3390/electronics11193089openalex-snapshot
Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs
inferred← citeshttps://doi.org/10.3390/electronics14030579openalex-snapshot
A Scalable Sorting Network Based on Hybrid Algorithms for Accelerating Data Sorting
inferred← citeshttps://doi.org/10.3390/jlpea12030038openalex-snapshot
Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm
inferred← citeshttps://doi.org/10.70675/805bde2dz11dez4a48z8f21z421629af4df5openalex-snapshot
Search for resonant Higgs boson pair production in the bbττ decay channel and developments in the reconstruction of High Granularity Calorimeter trigger primitives with the CMS detector at the LHC
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