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A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1088/1742-6596/1755/1/012008openalex-snapshot
Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture
inferredcites →https://doi.org/10.1093/qjmam/4.2.236openalex-snapshot
A SIGNED BINARY MULTIPLICATION TECHNIQUE
inferredcites →https://doi.org/10.1109/12.863039openalex-snapshot
High-speed Booth encoded parallel multiplier design
inferredcites →https://doi.org/10.1109/access.2020.3003684openalex-snapshot
A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism
inferredcites →https://doi.org/10.1109/aicas54282.2022.9869969openalex-snapshot
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing
inferredcites →https://doi.org/10.1109/aina.2012.99openalex-snapshot
Experimental Evaluation of Alkaline Batteries's Capacity for Low Power Consuming Applications
inferredcites →https://doi.org/10.1109/apccas.2004.1412685openalex-snapshot
Design of reconfigurable array multipliers and multiplier-accumulators
inferredcites →https://doi.org/10.1109/arith.2019.00029openalex-snapshot
A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/austrochip.2014.6946314openalex-snapshot
Evaluation of the back-end design overhead for ASIC implementations of large-operand multipliers targeting resource-constrained environments
inferredcites →https://doi.org/10.1109/icsccn.2011.6024609openalex-snapshot
Low power reconfigurable multiplier with reordering of partial products
inferredcites →https://doi.org/10.1109/iscas.2005.1464922openalex-snapshot
A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating
inferredcites →https://doi.org/10.1109/jssc.2004.835815openalex-snapshot
A dynamic scaling FFT processor for DVB-T applications
inferredcites →https://doi.org/10.1109/jssc.2008.920320openalex-snapshot
A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems
inferredcites →https://doi.org/10.1109/rteict.2017.8256771openalex-snapshot
ASIC realization and performance evaluation of 64×64 bit high speed multiplier in CMOS 45nm using Wallace Tree
inferredcites →https://doi.org/10.1109/spin.2017.8049986openalex-snapshot
An efficient VLSI architecture for iterative logarithmic multiplier
inferredcites →https://doi.org/10.1109/tc.2005.147openalex-snapshot
Low-complexity bit-parallel systolic Montgomery multipliers for special classes of GF(2/sup m/)
inferredcites →https://doi.org/10.1109/tc.2005.51openalex-snapshot
High-performance low-power left-to-right array multiplier design
inferredcites →https://doi.org/10.1109/tc.2009.89openalex-snapshot
Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers
inferredcites →https://doi.org/10.1109/tcsi.2009.2023763openalex-snapshot
Design of Power-Efficient Configurable Booth Multiplier
inferredcites →https://doi.org/10.1109/tpel.2019.2894465openalex-snapshot
Review of Power Conversion and Energy Management for Low-Power, Low-Voltage Energy Harvesting Powered Wireless Sensors
inferredcites →https://doi.org/10.1109/tvlsi.2008.2004544openalex-snapshot
BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture
inferredcites →https://doi.org/10.1109/tvlsi.2013.2252032openalex-snapshot
32 Bit $\times\,$32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler
inferredcites →https://doi.org/10.1145/263272.263337openalex-snapshot
Minimizing energy dissipation in high-speed multipliers
inferredcites →https://doi.org/10.1587/elex.16.20190212openalex-snapshot
Design of low-power low-area asynchronous iterative multiplier
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-032-30954-9_33openalex-snapshot
HIPA-SA: A Hybrid Precision-Aware Approximate Systolic Array Approach for Energy-Efficient ML Inference
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2024.109533openalex-snapshot
IoT-driven optimization of a NxN enhanced pipeline multiplier
inferred← citeshttps://doi.org/10.3390/app15094621openalex-snapshot
Very-Large-Scale Integration (VLSI) Implementation and Performance Comparison of Multiplier Topologies for Fixed- and Floating-Point Numbers
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