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https://doi.org/10.2139/ssrn.4671147

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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/icces57224.2023.10192881openalex-extracted
Design and Analysis of 4*4-Bit Vedic Multiplier with 32nm CNFET Technology
inferredcites →https://doi.org/10.1109/pedstc52094.2021.9405855openalex-extracted
Design and Implementation of A Transformerless High Step-Up DC-DC Converter Based on Conventional Boost Converter and Voltage Multiplier Cells
inferredcites →https://doi.org/10.3390/electronics11111721openalex-extracted
Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation
inferredcites →https://doi.org/10.3390/electronics11172685openalex-extracted
A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure
inferredcites →https://doi.org/10.3390/electronics11223712openalex-extracted
A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation
inferredcites →https://doi.org/10.3390/electronics11244202openalex-extracted
High-Speed Grouping and Decomposition Multiplier for Binary Multiplication
inferredcites →https://doi.org/10.3390/electronics12020446openalex-extracted
Design of Generalized Enhanced Static Segment Multiplier with Minimum Mean Square Error for Uniform and Nonuniform Input Distributions
inferredcites →https://doi.org/10.3390/electronics12143189openalex-extracted
Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata
inferredcites →https://doi.org/10.3390/electronics12153209openalex-extracted
Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier
inferredcites →https://doi.org/10.3390/electronics12153241openalex-extracted
A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices
inferredcites →https://doi.org/10.3390/electronics12194110openalex-extracted
Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices
inferredcites →https://doi.org/10.3390/s22052057openalex-extracted
Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems
inferredcites →https://doi.org/10.3390/s22062090openalex-extracted
Compact Finite Field Multiplication Processor Structure for Cryptographic Algorithms in IoT Devices with Limited Resources
inferredcites →https://doi.org/10.3390/s23094297openalex-extracted
Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration
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