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Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

https://doi.org/10.3390/electronics12143189

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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A New Coplanar Design of Multiplier Based on Nanoscale Quantum-Dot Cellular Automata

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Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder–subtractor using QCA technology

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Restoring and non-restoring array divider designs in Quantum-dot Cellular Automata

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A unique structure for the multiplexer in quantum-dot cellular automata to create a revolution in design of nanostructures

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Towards a molecular QCA wire: simulation of write-in and read-out systems

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Design of non‐restoring binary array divider in majority logic‐based QCA

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Design of non‐restoring divider in quantum‐dot cellular automata technology

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QCA circuit design of n ‐bit non‐restoring binary array divider

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Design of non‐restoring binary array divider in quantum‐dot cellular automata

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Power gain and dissipation in quantum-dot cellular automata

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Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling

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Reliable adder and multipliers in QCA technology

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Computer arithmetic structures for quantum cellular automata

inferredcites →https://doi.org/10.1109/acssc.2012.6489269openalex-snapshot

Modified non-restoring division algorithm with improved delay profile and error correction

inferredcites →https://doi.org/10.1109/ecctd.2007.4529752openalex-snapshot

Pipelined array multiplier based on quantum-dot cellular automata

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Implementation of 4×4 vedic multiplier using carry save adder in quantum-dot cellular automata

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High Speed Memory Cell with Data Integrity in QCA

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Non-restoring QCA array divider using CIXOR functional gate

inferredcites →https://doi.org/10.1109/iciset54810.2022.9775903openalex-snapshot

Area-Efficient Design of a Quantum-Dot Cellular Automata Based Full Adder Having Low Latency

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QCA Systolic Matrix Multiplier

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A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells

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Carbon Nanotubes for High-Performance Electronics—Progress and Prospect

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High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/nano.2011.6144359openalex-snapshot

Restoring divider design for quantum-dot cellular automata

inferredcites →https://doi.org/10.1109/taes.2020.2982341openalex-snapshot

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace Applications

inferredcites →https://doi.org/10.1109/tcad.2018.2789782openalex-snapshot

An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tcsii.2016.2580901openalex-snapshot

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tcsii.2017.2703942openalex-snapshot

Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tcsii.2018.2873797openalex-snapshot

Design of an Efficient Multilayer Arithmetic Logic Unit in Quantum-Dot Cellular Automata (QCA)

inferredcites →https://doi.org/10.1109/tcsii.2018.2878717openalex-snapshot

New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tcsii.2019.2953866openalex-snapshot

Design of QCA-Serial Parallel Multiplier (QSPM) With Energy Dissipation Analysis

inferredcites →https://doi.org/10.1109/tcsii.2020.2989496openalex-snapshot

A Novel XOR/XNOR Structure for Modular Design of QCA Circuits

inferredcites →https://doi.org/10.1109/tcsii.2020.3047393openalex-snapshot

BCD Adder Designs Based on Three-Input XOR and Majority Gates

inferredcites →https://doi.org/10.1109/tcsii.2021.3077669openalex-snapshot

Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA

inferredcites →https://doi.org/10.1109/tcsii.2021.3107630openalex-snapshot

Efficient Design of Vedic Square Calculator Using Quantum Dot Cellular Automata (QCA)

inferredcites →https://doi.org/10.1109/tcsii.2022.3171848openalex-snapshot

Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tcsii.2022.3193561openalex-snapshot

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tcsii.2023.3237695openalex-snapshot

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tnano.2003.820815openalex-snapshot

QCADesigner: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata

inferredcites →https://doi.org/10.1109/tnano.2005.858591openalex-snapshot

Organic thin-film transistors using pentacene and SiOC film

inferredcites →https://doi.org/10.1109/tnano.2019.2910823openalex-snapshot

Electric-Field Inputs for Molecular Quantum-Dot Cellular Automata Circuits

inferredcites →https://doi.org/10.1109/tnano.2020.2969166openalex-snapshot

Design of an Efficient N × N Butterfly Switching Network in Quantum-Dot Cellular Automata (QCA)

inferredcites →https://doi.org/10.1109/tnano.2020.3048729openalex-snapshot

Low-Energy Eigenspectrum Decomposition (LEED) of Quantum-Dot Cellular Automata Networks

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Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications

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Robust Electric-Field Input Circuits for Clocked Molecular Quantum-Dot Cellular Automata

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Majority Logic Gate for Magnetic Quantum-Dot Cellular Automata

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Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

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Non-Restoring Array Divider Using Optimized CAS Cells Based on Quantum-Dot Cellular Automata with Minimized Latency and Power Dissipation for Quantum Computing

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A nano-scale design of arithmetic and logic unit for energy-efficient signal processing devices based on a quantum-based technology

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IoT-driven optimization of a NxN enhanced pipeline multiplier

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Design and implementation of a nano-scale high-speed multiplier for signal processing applications

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High-speed and area-efficient arithmetic and logic unit architecture using quantum-dot cellular automata for digital signal processing

inferred← citeshttps://doi.org/10.1016/j.vlsi.2026.102714openalex-snapshot

Layout optimization and physical verification of complex quantum-dot cellular automata circuits for high-performance computing

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Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells

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Design and implementation of a nano-scale digital adder for quantum-based signal processing applications

inferred← citeshttps://doi.org/10.1088/1402-4896/add2aeopenalex-snapshot

An energy and cost-effective realization of high-performance single-layer vedic multiplier in quantum-dot cellular automata

inferred← citeshttps://doi.org/10.1109/icee70628.2026.11710453openalex-snapshot

A Novel Design of Efficient Coplanar $2 \times 2$ QCA Multiplier with Energy Analysis

inferred← citeshttps://doi.org/10.1109/icicacs65178.2025.10968849openalex-snapshot

Design & Development of Multipliers & Square Circuits Using the Concepts of Quantum-Dot Cellular Automata (QCA) Technology

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Design of Reversible Quantum Vigenere Cryptographic Cipher in QCA and IBMQ Platforms for Secure Nanocommunication

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Coplanar High‐Speed and Efficient Multiplier Design for QCA Technology

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Design of optimized reversible multipliers using KMD gates for DSP applications

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