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Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/cta.4490200402openalex-snapshot
Theory of Transmission Switches and Its Application to Design of CMOS Digital Circuits
inferredcites →https://doi.org/10.1007/s00034-019-01044-xopenalex-snapshot
Low-Cost and High-Performance 8 × 8 Booth Multiplier
inferredcites →https://doi.org/10.1049/el:19690201openalex-snapshot
Fully iterative fast array for binary multiplication and addition
inferredcites →https://doi.org/10.1049/ip-g-1.1988.0019openalex-snapshot
Parallel architecture modified Booth multiplier
inferredcites →https://doi.org/10.1080/00207218808945289openalex-snapshot
Design of ternary CMOS circuits based on transmission function theory
inferredcites →https://doi.org/10.1088/1757-899x/1065/1/012047openalex-snapshot
Comparison between CMOS full adder and PTL full adder
inferredcites →https://doi.org/10.1093/qjmam/4.2.236openalex-snapshot
A SIGNED BINARY MULTIPLICATION TECHNIQUE
inferredcites →https://doi.org/10.1109/4.149426openalex-snapshot
A 54*54-b regularly structured tree multiplier
inferredcites →https://doi.org/10.1109/82.466647openalex-snapshot
Use of minimum-adder multiplier blocks in FIR digital filters
inferredcites →https://doi.org/10.1109/82.686699openalex-snapshot
IIR digital filter design using minimum adder multiplier blocks
inferredcites →https://doi.org/10.1109/92.238424openalex-snapshot
M*N Booth encoded multiplier generator using optimized Wallace trees
inferredcites →https://doi.org/10.1109/icccnt45670.2019.8944888openalex-snapshot
A Novel Hybrid Full Adder Based on Gate Diffusion Input Technique, Transmission Gate and Static CMOS Logic
inferredcites →https://doi.org/10.1109/iccd.1997.628913openalex-snapshot
A universal Pezaris array multiplier generator for SRAM-based FPGAs
inferredcites →https://doi.org/10.1109/icetet.2008.25openalex-snapshot
ASIC Implementation of 4 Bit Multipliers
inferredcites →https://doi.org/10.1109/icias.2007.4658609openalex-snapshot
Low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic
inferredcites →https://doi.org/10.1109/isvdat.2015.7208143openalex-snapshot
Implementation of a high speed multiplier for high-performance and low power applications
inferredcites →https://doi.org/10.1109/jrproc.1961.287779openalex-snapshot
High-Speed Arithmetic in Binary Computers
inferredcites →https://doi.org/10.1109/mwscas.1996.594049openalex-snapshot
A multiplier and squarer generator for high performance DSP applications
inferredcites →https://doi.org/10.1109/sips.1999.822379openalex-snapshot
A 14-transistor CMOS full adder with full voltage-swing nodes
inferredcites →https://doi.org/10.1109/tc.1979.1675350openalex-snapshot
Global and Modular Two's Complement Cellular Array Multipliers
inferredcites →https://doi.org/10.1109/tcsii.2011.2111610openalex-snapshot
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications
inferredcites →https://doi.org/10.1109/tencon.2017.8227834openalex-snapshot
A proposed reliable and power efficient 14T full adder circuit design
inferredcites →https://doi.org/10.1109/tencon.2018.8650108openalex-snapshot
Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier
inferredcites →https://doi.org/10.1109/tvlsi.2016.2643639openalex-snapshot
Design of Power and Area Efficient Approximate Multipliers
inferredcites →https://doi.org/10.1155/2000/34760openalex-snapshot
Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors
inferredcites →https://doi.org/10.35940/ijitee.c8891.029420openalex-snapshot
Design and Implementation of Full Adder using Different XOR Gates
inferredcites →https://doi.org/10.3923/jas.2006.1978.1981openalex-snapshot
A Novel Low Power and High Performance 14 Transistor CMOS Full Adder Cell
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-981-95-0705-4_15openalex-snapshot
A 14 T Low-Power High-Speed Full Adder Circuit
inferred← citeshttps://doi.org/10.1007/s10470-026-02630-1openalex-snapshot
FPGA Implementation and Performance Enhancement of FIR Filter with Hybrid FinFET-GDI logic based Carry Select Adder
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2024.109533openalex-snapshot
IoT-driven optimization of a NxN enhanced pipeline multiplier
inferred← citeshttps://doi.org/10.1016/j.measurement.2025.116691openalex-snapshot
Area efficient low power VLSI of 2048-Point pipelined radix 16 MDC /FFT Processer for brain tumour detection using optimized deep dilated convolutional neural network
inferred← citeshttps://doi.org/10.1016/j.vlsi.2026.102854openalex-snapshot
Accelerated impulse noise detection with approximate and in-memory computing techniques
inferred← citeshttps://doi.org/10.1109/aespc67542.2025.11326720openalex-snapshot
Speed and Power Optimized Pass Transistor Logic Multiplier Using Cascaded Compressor
inferred← citeshttps://doi.org/10.1109/ccpis65231.2025.11234200openalex-snapshot
Energy-Efficient Low-Latency Approximate Multiplier using FPGA for Image Processing
inferred← citeshttps://doi.org/10.1109/cnc68716.2025.11484634openalex-snapshot
Power-Efficient Hybrid Full Adder Design For Battery Management Systems
inferred← citeshttps://doi.org/10.1109/devic63749.2025.11012577openalex-snapshot
High Speed 16T DPTL Full Adder with Reduced Power Dissipation
inferred← citeshttps://doi.org/10.1109/edct65302.2025.11495703openalex-snapshot
Power-Efficient Dadda Multiplier Using 9:2 Compressor for Retinal Image Processing
inferred← citeshttps://doi.org/10.1109/edct65302.2025.11496112openalex-snapshot
Energy-Efficient Transmission Gate-Based Full Adder for Advanced VLSI Systems
inferred← citeshttps://doi.org/10.1109/iccies63851.2025.11032610openalex-snapshot
Design Of Low Power Eight Bit Signed Wallace Tree Multiplier For FIR Filter
inferred← citeshttps://doi.org/10.1109/icdcot61034.2024.10515488openalex-snapshot
Analysis of CMOS Full Adder Circuits for Multiplier Logic Architectures
inferred← citeshttps://doi.org/10.1109/icicv64824.2025.11085878openalex-snapshot
Shannon Adder-based 8×8 Multiplier with Power and Error Optimization
inferred← citeshttps://doi.org/10.1109/icimia67127.2025.11200617openalex-snapshot
Design and Analysis of a 4-Bit Ripple Carry Adder using CMOS 90nm Technology in Microwind
inferred← citeshttps://doi.org/10.1109/iecct68664.2026.11541640openalex-snapshot
A Power Optimized 32-Bit Carry Look Ahead Adder Employing PTL and NMOS Power Gated Technique for VLSI Circuits
inferred← citeshttps://doi.org/10.1109/ises67504.2025.00047openalex-snapshot
Design and Integration of High-Efficiency Full Adder Design Using Pass Transistor Logic
inferred← citeshttps://doi.org/10.1109/newcas64543.2026.11674025openalex-snapshot
EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring
inferred← citeshttps://doi.org/10.1109/tcsi.2025.3566232openalex-snapshot
A Self-Decryption Pass Transistor Logic-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET
inferred← citeshttps://doi.org/10.1109/tcsii.2024.3366169openalex-snapshot
Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style
inferred← citeshttps://doi.org/10.1134/s1063739724600791openalex-snapshot
Leveraging 7-nm FinFET Technology for 1-Bit Full Adder Design: Comprehensive Analysis for Smart Applications
inferred← citeshttps://doi.org/10.22214/ijraset.2024.58495openalex-snapshot
Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits
inferred← citeshttps://doi.org/10.3390/electronics13071284openalex-snapshot
Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model
inferred← citeshttps://doi.org/10.53314/els2630055sopenalex-snapshot
Low Power CNTFET 3-Transistor Approximate Full Adder for Real-Time Edge Image Processing
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