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Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s13389-022-00302-0openalex-snapshot
Low area-time complexity point multiplication architecture for ECC over GF($$2^{\textrm{m}}$$) using polynomial basis
inferredcites →https://doi.org/10.1016/j.mejo.2016.03.006openalex-snapshot
High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems
inferredcites →https://doi.org/10.1049/iet-cds.2017.0300openalex-snapshot
Efficient digit‐serial modular multiplication algorithm on FPGA
inferredcites →https://doi.org/10.1049/iet-cdt.2018.5056openalex-snapshot
Throughput/area optimised pipelined architecture for elliptic curve crypto processor
inferredcites →https://doi.org/10.1109/81.841927openalex-snapshot
Clock-gating and its application to low power design of sequential circuits
inferredcites →https://doi.org/10.1109/access.2022.3141104openalex-snapshot
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor
inferredcites →https://doi.org/10.1109/icecs49266.2020.9294908openalex-snapshot
An Area Aware Accelerator for Elliptic Curve Point Multiplication
inferredcites →https://doi.org/10.1109/iscas.2012.6271889openalex-snapshot
Design of a low-cost low-power baseband-processor for UHF RFID tag with asynchronous design technique
inferredcites →https://doi.org/10.1109/tcsi.2017.2677962openalex-snapshot
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over $GF(2^{m})$ Based on NIST Polynomials
inferredcites →https://doi.org/10.1109/tcsi.2018.2866248openalex-snapshot
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm
inferredcites →https://doi.org/10.1109/tcsii.2015.2455992openalex-snapshot
Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA
inferredcites →https://doi.org/10.1109/tie.2012.2186104openalex-snapshot
Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations
inferredcites →https://doi.org/10.1109/tvlsi.2015.2453360openalex-snapshot
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)
inferredcites →https://doi.org/10.1109/tvlsi.2016.2574620openalex-snapshot
High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA
inferredcites →https://doi.org/10.1109/tvlsi.2021.3058509openalex-snapshot
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation
inferredcites →https://doi.org/10.1109/tvlsi.2023.3268999openalex-snapshot
Speed/Area-Efficient ECC Processor Implementation Over GF(2 m ) on FPGA via Novel Algorithm-Architecture Co-Design
inferredcites →https://doi.org/10.1145/3310354openalex-snapshot
FPGA Implementation of the ECC Over GF(2 m ) for Small Embedded Applications
inferredcites →https://doi.org/10.1201/9781439821916openalex-snapshot
Handbook of Applied Cryptography
inferredcites →https://doi.org/10.3390/app13031240openalex-snapshot
Large Field-Size Elliptic Curve Processor for Area-Constrained Applications
inferredcites →https://doi.org/10.3390/app13127018openalex-snapshot
Area-Efficient Realization of Binary Elliptic Curve Point Multiplication Processor for Cryptographic Applications
inferredcites →https://doi.org/10.3390/app13158633openalex-snapshot
A Crypto Accelerator of Binary Edward Curves for Securing Low-Resource Embedded Devices
inferredcites →https://doi.org/10.3390/electronics10111252openalex-snapshot
FPGA Implementation of High-Efficiency ECC Point Multiplication Circuit
inferredcites →https://doi.org/10.3390/electronics12153241openalex-snapshot
A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices
inferredcites →https://doi.org/10.3390/s141017883openalex-snapshot
Design of an Elliptic Curve Cryptography Processor for RFID Tag Chips
inferredcites →https://doi.org/10.3390/s20185148openalex-snapshot
Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve
inferredcites →https://doi.org/10.3390/s20185350openalex-snapshot
A Lightweight Authentication and Key Agreement Schemes for IoT Environments
inferredcites →https://doi.org/10.3390/s21041451openalex-snapshot
High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA
inferredcites →https://doi.org/10.3390/s22072561openalex-snapshot
Revisiting the Feasibility of Public Key Cryptography in Light of IIoT Communications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2024.109533openalex-snapshot
IoT-driven optimization of a NxN enhanced pipeline multiplier
inferred← citeshttps://doi.org/10.3390/info16090773openalex-snapshot
Hardware Validation for Semi-Coherent Transmission Security
inferred← citeshttps://doi.org/10.3390/jsan14050086openalex-snapshot
Efficient and Low-Cost Modular Polynomial Multiplier for WSN Security
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