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Distributed-Memory-Based FFT Architecture and FPGA Implementations
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4020-6629-0openalex-snapshot
Fast Fourier Transform - Algorithms and Applications
inferredcites →https://doi.org/10.1007/978-3-642-03882-2_502openalex-snapshot
Evaluation of Parallel FFT Implementations on GPU and Multi-core PCs for Magnetic Induction Tomography
inferredcites →https://doi.org/10.1007/s00034-015-9990-yopenalex-snapshot
Triple-Matrix Product-Based 2D Systolic Implementation of Discrete Fourier Transform
inferredcites →https://doi.org/10.1016/0743-7315(89)90026-9openalex-snapshot
Systematic algorithm mapping for multidimensional systolic arrays
inferredcites →https://doi.org/10.1049/sbra021eopenalex-snapshot
Principles of Modern Radar: Basic principles
inferredcites →https://doi.org/10.1109/11.992857openalex-snapshot
Design of a 3780-point IFFT processor for TDS-OFDM
inferredcites →https://doi.org/10.1109/78.215326openalex-snapshot
A new systolic realization for the discrete Fourier transform
inferredcites →https://doi.org/10.1109/hpec.2014.7040997openalex-snapshot
Design of 3D FFTs with FPGA clusters
inferredcites →https://doi.org/10.1109/icapp.1995.472165openalex-snapshot
A new expandable 2D systolic array for DFT computation based on symbiosis of 1D arrays
inferredcites →https://doi.org/10.1109/icassp.2007.366162openalex-snapshot
A New Class of High Performance FFTs
inferredcites →https://doi.org/10.1109/iccnc.2014.6785453openalex-snapshot
High-throughput programmable systolic array FFT architecture and FPGA implementations
inferredcites →https://doi.org/10.1109/icetc.2010.5529796openalex-snapshot
Design of fixed-point high-performance FFT processor
inferredcites →https://doi.org/10.1109/iscas.2009.5117960openalex-snapshot
The design of a reconfigurable continuous-flow mixed-radix FFT processor
inferredcites →https://doi.org/10.1109/ised.2012.47openalex-snapshot
Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution
inferredcites →https://doi.org/10.1109/jproc.2014.2386883openalex-snapshot
Reconfigurable Computing Architectures
inferredcites →https://doi.org/10.1109/jproc.2015.2392104openalex-snapshot
Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology
inferredcites →https://doi.org/10.1109/samos.2013.6621101openalex-snapshot
A scalable FFT processor architecture for OFDM based communication systems
inferredcites →https://doi.org/10.1109/sips.2006.352556openalex-snapshot
Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems
inferredcites →https://doi.org/10.1109/tce.2006.1605021openalex-snapshot
An approach to simplify the design of IFFT/FFT cores for OFDM systems
inferredcites →https://doi.org/10.1109/tcsii.2017.2683643openalex-snapshot
A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors
inferredcites →https://doi.org/10.1109/tii.2015.2431223openalex-snapshot
Advanced Features and Industrial Applications of FPGAs—A Review
inferredcites →https://doi.org/10.1109/tsp.2005.859216openalex-snapshot
Computationally efficient systolic architecture for computing the discrete Fourier transform
inferredcites →https://doi.org/10.1109/tvlsi.2011.2178275openalex-snapshot
Pipelined Radix-$2^{k}$ Feedforward FFT Architectures
inferredcites →https://doi.org/10.1109/tvlsi.2013.2259512openalex-snapshot
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects
inferredcites →https://doi.org/10.1109/tvlsi.2016.2567784openalex-snapshot
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
inferredcites →https://doi.org/10.1109/tvlsi.2017.2710479openalex-snapshot
Efficient FPGA Mapping of Pipeline SDF FFT Cores
inferredcites →https://doi.org/10.1109/wcnc.2007.442openalex-snapshot
A High Performance Scalable FFT
inferredcites →https://doi.org/10.1109/wcnc.2012.6214486openalex-snapshot
High throughput and hardware efficient FFT architecture for LTE application
inferredcites →https://doi.org/10.1201/9780367806934openalex-snapshot
Computer Simulation Using Particles
inferredcites →https://doi.org/10.23919/icact.2017.7890190openalex-snapshot
An area-efficient multimode FFT circuit for IEEE 802.11 ax WLAN devices
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s00034-022-02012-8openalex-snapshot
Design of the Processors for Fast Cosine and Sine Fourier Transforms
inferred← citeshttps://doi.org/10.1007/s11277-020-07471-3openalex-snapshot
Optimized Pipelined Fast Fourier Transform Using Split and Merge Parallel Processing Units for OFDM
inferred← citeshttps://doi.org/10.1080/00207217.2020.1819441openalex-snapshot
Hardware chip performance analysis of different FFT architecture
inferred← citeshttps://doi.org/10.1109/access.2025.3648787openalex-snapshot
Design Space Exploration of FFT Architectures and Numerical Formats for SoC-Based FMCW Radar Signal Processing
inferred← citeshttps://doi.org/10.1186/s13634-020-00692-5openalex-snapshot
Using the complement of the cosine to compute trigonometric functions
inferred← citeshttps://doi.org/10.3390/computation7040063openalex-snapshot
Field Programmable Gate Array Applications—A Scientometric Review
inferred← citeshttps://doi.org/10.3390/electronics8050584openalex-snapshot
Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs
inferred← citeshttps://doi.org/10.3390/jlpea13030045openalex-snapshot
BFT—Low-Latency Bit-Slice Design of Discrete Fourier Transform
inferred← citeshttps://doi.org/10.3390/s22052027openalex-snapshot
Design of a Supraharmonic Monitoring System Based on an FPGA Device
inferred← citeshttps://doi.org/10.3906/elk-2101-56openalex-snapshot
HC-FFT: highly configurable and efficient FFT implementation on FPGA
inferred← citeshttps://doi.org/10.46387/bjesr.1233679openalex-snapshot
A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM
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