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Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

https://doi.org/10.3390/electronics8050584

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s00034-014-9796-3openalex-snapshot

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

inferredcites →https://doi.org/10.1007/s00034-017-0628-0openalex-snapshot

Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells

inferredcites →https://doi.org/10.1109/access.2017.2756702openalex-snapshot

G-AETCAM: Gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA

inferredcites →https://doi.org/10.1109/access.2018.2816039openalex-snapshot

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation

inferredcites →https://doi.org/10.1109/access.2018.2822311openalex-snapshot

Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA

inferredcites →https://doi.org/10.1109/access.2018.2854306openalex-snapshot

Fast Pattern Recognition Through an LBP Driven CAM on FPGA

inferredcites →https://doi.org/10.1109/ancs.2013.6665177openalex-snapshot

Scalable Ternary Content Addressable Memory implementation using FPGAs

inferredcites →https://doi.org/10.1109/jproc.2015.2434888openalex-snapshot

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

inferredcites →https://doi.org/10.1109/les.2017.2664378openalex-snapshot

LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA

inferredcites →https://doi.org/10.1109/les.2017.2770225openalex-snapshot

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA

inferredcites →https://doi.org/10.1109/les.2018.2888889openalex-snapshot

Beyond the Limits of Typical Strategies: Resources Efficient FPGA-Based TCAM

inferredcites →https://doi.org/10.1109/tcsi.2012.2215736openalex-snapshot

Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory

inferredcites →https://doi.org/10.1109/tcsi.2016.2584658openalex-snapshot

Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing

inferredcites →https://doi.org/10.1109/tcsii.2015.2504946openalex-snapshot

Energy-Efficient Associative Memory Based on Neural Cliques

inferredcites →https://doi.org/10.1109/tcsii.2016.2595598openalex-snapshot

Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage

inferredcites →https://doi.org/10.1109/tencon.2015.7372837openalex-snapshot

UE-TCAM: An ultra efficient SRAM-based TCAM

inferredcites →https://doi.org/10.1109/tnet.2018.2820067openalex-snapshot

Memory-Efficient and Ultra-Fast Network Lookup and Forwarding Using Othello Hashing

inferredcites →https://doi.org/10.1109/tvlsi.2014.2309350openalex-snapshot

Z-TCAM: An SRAM-based Architecture for TCAM

inferredcites →https://doi.org/10.1109/tvlsi.2016.2518219openalex-snapshot

Precharge-Free, Low-Power Content-Addressable Memory

inferredcites →https://doi.org/10.1109/tvlsi.2016.2636294openalex-snapshot

Resource-Efficient SRAM-Based Ternary Content Addressable Memory

inferredcites →https://doi.org/10.1109/tvlsi.2018.2809644openalex-snapshot

High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing

inferredcites →https://doi.org/10.1109/tvlsi.2019.2891507openalex-snapshot

Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor

inferredcites →https://doi.org/10.1109/tvlsi.2019.2904105openalex-snapshot

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

inferredcites →https://doi.org/10.1587/transele.e97.c.65openalex-snapshot

A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA

inferredcites →https://doi.org/10.3390/electronics4041062openalex-snapshot

Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs

inferredcites →https://doi.org/10.3390/electronics5010010openalex-snapshot

FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems

inferredcites →https://doi.org/10.3390/electronics7070116openalex-snapshot

Distributed-Memory-Based FFT Architecture and FPGA Implementations

inferredcites →https://doi.org/10.3390/electronics7090186openalex-snapshot

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

inferredcites →https://doi.org/10.3390/jlpea8030025openalex-snapshot

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

inferredcites →https://doi.org/10.5555/2537857.2537867openalex-snapshot

Scalable ternary content addressable memory implementation using FPGAs

inferredcites →https://doi.org/10.7567/jjap.57.04ff11openalex-snapshot

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11227-023-05357-2openalex-snapshot

Using FPGA-based content-addressable memory for mnemonics instruction searching in assembler design

inferred← citeshttps://doi.org/10.1016/j.dcan.2022.04.010openalex-snapshot

Efficient pipelined flow classification for intelligent data processing in IoT

inferred← citeshttps://doi.org/10.1016/j.future.2021.09.037openalex-snapshot

Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey

inferred← citeshttps://doi.org/10.1080/00207217.2026.2637035openalex-snapshot

Low power content-addressable memory for FPGA implementation

inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132888openalex-snapshot

Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408550openalex-snapshot

NP-CAM: Efficient and Scalable DNA Classification using a NoC-Partitioned CAM Architecture

inferred← citeshttps://doi.org/10.1109/icesc57686.2023.10193436openalex-snapshot

Comparative Analysis of Power and Hardware Utilization in an Energy-Efficient 8:3 Encoder

inferred← citeshttps://doi.org/10.1109/icjece.2020.3025198openalex-snapshot

Fast Mapping and Updating Algorithms for a Binary CAM on FPGA

inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043294openalex-snapshot

A Resource-efficient Dually-addressable Memory Architecture on FPGA

inferred← citeshttps://doi.org/10.1109/msn48538.2019.00068openalex-snapshot

High Performance Power-Efficient Gate-Based CAM for Reconfigurable Computing

inferred← citeshttps://doi.org/10.1145/3466823openalex-snapshot

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

inferred← citeshttps://doi.org/10.1155/2020/7641073openalex-snapshot

A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things

inferred← citeshttps://doi.org/10.1155/2020/8843471openalex-snapshot

A Fast, Smart Packet Classification Algorithm Based on Decomposition

inferred← citeshttps://doi.org/10.1515/chem-2022-0258openalex-snapshot

BiCAM-based automated scoring system for digital logic circuit diagrams

inferred← citeshttps://doi.org/10.21203/rs.3.rs-1740224/v1openalex-snapshot

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

inferred← citeshttps://doi.org/10.26634/jele.14.1.20441openalex-snapshot

A High-Performance Dual Classifier Based Packet Classification Engine On Fpga

inferred← citeshttps://doi.org/10.32604/cmc.2022.020529openalex-snapshot

Dual-Port Content Addressable Memory for Cache Memory Applications

inferred← citeshttps://doi.org/10.3390/app112311164openalex-snapshot

AxP: A HW-SW Co-Design Pipeline for Energy-Efficient Approximated ConvNets via Associative Matching

inferred← citeshttps://doi.org/10.3390/electronics14091765openalex-snapshot

HLSCAM: Fine-Tuned HLS-Based Content Addressable Memory Implementation for Packet Processing on FPGA

inferred← citeshttps://doi.org/10.46387/bjesr.1233679openalex-snapshot

A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM

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