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Efficient Implementation of 2D and 3D Sparse Deconvolutional Neural Networks with a Uniform Architecture on FPGAs

https://doi.org/10.3390/electronics8070803

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-319-46475-6_25openalex-snapshot

Accelerating the Super-Resolution Convolutional Neural Network

inferredcites →https://doi.org/10.1109/3dv.2016.79openalex-snapshot

V-Net: Fully Convolutional Neural Networks for Volumetric Medical Image Segmentation

inferredcites →https://doi.org/10.1109/cvpr.2015.7298965openalex-snapshot

Fully convolutional networks for semantic segmentation

inferredcites →https://doi.org/10.1109/fccm.2018.00019openalex-snapshot

FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks

inferredcites →https://doi.org/10.1109/fpt.2016.7929549openalex-snapshot

Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/iccd.2016.7753296openalex-snapshot

CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks

inferredcites →https://doi.org/10.1109/isca.2018.00060openalex-snapshot

GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks

inferredcites →https://doi.org/10.1109/iscas.2019.8702780openalex-snapshot

Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs

inferredcites →https://doi.org/10.1109/mocast.2018.8376612openalex-snapshot

Expanding a robot's life: Low power object recognition via FPGA-based DCNN deployment

inferredcites →https://doi.org/10.1109/ngcas.2017.16openalex-snapshot

A Convolutional Neural Network Fully Implemented on FPGA for Embedded Platforms

inferredcites →https://doi.org/10.1109/tcad.2018.2857258openalex-snapshot

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration

inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

inferredcites →https://doi.org/10.1145/2847263.2847265openalex-snapshot

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network

inferredcites →https://doi.org/10.1145/3079758openalex-snapshot

Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks

inferredcites →https://doi.org/10.1145/3289602.3293905openalex-snapshot

Reconfigurable Convolutional Kernels for Neural Networks on FPGAs

inferredcites →https://doi.org/10.48550/arxiv.1510.00149openalex-snapshot

Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding

inferredcites →https://doi.org/10.48550/arxiv.1610.07584openalex-snapshot

Learning a Probabilistic Latent Space of Object Shapes via 3D Generative-Adversarial Modeling

inferredcites →https://doi.org/10.48550/arxiv.1703.07195openalex-snapshot

GP-GAN: Towards Realistic High-Resolution Image Blending

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-20738-9_61openalex-snapshot

Research on FPGA Accelerator Optimization Based on Graph Neural Network

inferred← citeshttps://doi.org/10.1007/978-981-19-6901-0_60openalex-snapshot

FPGA Implementation of Column-Wise Deconvolution Accelerator Based on Structural Optimization for Medical Image Segmentation

inferred← citeshttps://doi.org/10.1007/s11265-023-01883-7openalex-snapshot

FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis

inferred← citeshttps://doi.org/10.1088/2634-4386/ac7c8aopenalex-snapshot

Two sparsities are better than one: unlocking the performance benefits of sparse–sparse networks

inferred← citeshttps://doi.org/10.1109/access.2020.3048375openalex-snapshot

Binarized Encoder-Decoder Network and Binarized Deconvolution Engine for Semantic Segmentation

inferred← citeshttps://doi.org/10.1109/hipc53243.2021.00022openalex-snapshot

How to Avoid Zero-Spacing in Fractionally-Strided Convolution? A Hardware-Algorithm Co-Design Methodology

inferred← citeshttps://doi.org/10.1109/icmisi65108.2025.11115469openalex-snapshot

Semi-Structured Sparsity Using Dynamic Percentile

inferred← citeshttps://doi.org/10.15587/1729-4061.2023.281731openalex-snapshot

Development of a model for determining the necessary FPGA computing resource for placing a multilayer neural network on it

inferred← citeshttps://doi.org/10.3390/electronics9010045openalex-snapshot

Quality Assessment of Tire Shearography Images via Ensemble Hybrid Faster Region-Based ConvNets

inferred← citeshttps://doi.org/10.3390/jimaging6090085openalex-snapshot

Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip

inferred← citeshttps://doi.org/10.3390/jimaging7100210openalex-snapshot

Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions

inferred← citeshttps://doi.org/10.3390/technologies8030046openalex-snapshot

Hardware Implementation of a Softmax-Like Function for Deep Learning

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