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BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs

https://doi.org/10.3390/electronics9020353
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s00034-014-9796-3openalex-snapshot
E-TCAM: An Efficient SRAM-Based Architecture for TCAM
inferredcites →https://doi.org/10.1016/j.comcom.2014.08.004openalex-snapshot
A multi-pipeline architecture for high-speed packet classification
inferredcites →https://doi.org/10.1016/j.comnet.2012.04.014openalex-snapshot
A new hierarchical packet classification algorithm
inferredcites →https://doi.org/10.1016/j.ipl.2019.03.008openalex-snapshot
CuCoTrack: Cuckoo filter based connection tracking
inferredcites →https://doi.org/10.1093/comjnl/bxy052openalex-snapshot
Fast Packet Classification using Recursive Endpoint-Cutting and Bucket Compression on FPGA
inferredcites →https://doi.org/10.1109/access.2017.2756702openalex-snapshot
G-AETCAM: Gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA
inferredcites →https://doi.org/10.1109/access.2018.2822311openalex-snapshot
Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA
inferredcites →https://doi.org/10.1109/ancs.2013.6665177openalex-snapshot
Scalable Ternary Content Addressable Memory implementation using FPGAs
inferredcites →https://doi.org/10.1109/hpsr.2018.8850764openalex-snapshot
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays
inferredcites →https://doi.org/10.1109/iccecome.2018.8658961openalex-snapshot
Impact of Initialization on Gate-Based Area Efficient Ternary Content-Addressable Memory
inferredcites →https://doi.org/10.1109/jssc.2005.864128openalex-snapshot
Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey
inferredcites →https://doi.org/10.1109/les.2017.2664378openalex-snapshot
LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA
inferredcites →https://doi.org/10.1109/les.2017.2770225openalex-snapshot
Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA
inferredcites →https://doi.org/10.1109/les.2018.2888889openalex-snapshot
Beyond the Limits of Typical Strategies: Resources Efficient FPGA-Based TCAM
inferredcites →https://doi.org/10.1109/lnet.2019.2897934openalex-snapshot
Pseudo-TCAM: SRAM-Based Architecture for Packet Classification in One Memory Access
inferredcites →https://doi.org/10.1109/mm.2005.8openalex-snapshot
Efficient Multimatch Packet Classification and Lookup with TCAM
inferredcites →https://doi.org/10.1109/mm.2014.61openalex-snapshot
NetFPGA SUME: Toward 100 Gbps as Research Commodity
inferredcites →https://doi.org/10.1109/reconfig.2014.7032536openalex-snapshot
Low power RAM-based hierarchical CAM on FPGA
inferredcites →https://doi.org/10.1109/tcsi.2012.2215736openalex-snapshot
Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory
inferredcites →https://doi.org/10.1109/tencon.2015.7372837openalex-snapshot
UE-TCAM: An ultra efficient SRAM-based TCAM
inferredcites →https://doi.org/10.1109/tvlsi.2011.2162112openalex-snapshot
Scalable Packet Classification on FPGA
inferredcites →https://doi.org/10.1109/tvlsi.2013.2241798openalex-snapshot
Ultra-High Throughput Low-Power Packet Classification
inferredcites →https://doi.org/10.1109/tvlsi.2014.2309350openalex-snapshot
Z-TCAM: An SRAM-based Architecture for TCAM
inferredcites →https://doi.org/10.1109/tvlsi.2016.2636294openalex-snapshot
Resource-Efficient SRAM-Based Ternary Content Addressable Memory
inferredcites →https://doi.org/10.1109/tvlsi.2019.2903980openalex-snapshot
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration
inferredcites →https://doi.org/10.1109/tvlsi.2019.2904105openalex-snapshot
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates
inferredcites →https://doi.org/10.1145/2486001.2486011openalex-snapshot
Forwarding metamorphosis
inferredcites →https://doi.org/10.3390/electronics7090186openalex-snapshot
EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA
inferredcites →https://doi.org/10.5555/2537857.2537867openalex-snapshot
Scalable ternary content addressable memory implementation using FPGAs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-981-16-8892-8_15openalex-snapshot
Adoption of Microstrip Antenna to Multiple Input Multiple Output Microstrip Antenna for Wireless Applications: A Review
inferred← citeshttps://doi.org/10.1007/s11227-022-04377-8openalex-snapshot
Hardware-based multi-match packet classification in NIDS: an overview and novel extensions for improving the energy efficiency of TCAM-based classifiers
inferred← citeshttps://doi.org/10.1007/s42835-026-02828-3openalex-snapshot
A Novel Packet Classifier Duo for Intrusion and Detection Systems Using Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1109/ichci51889.2020.00016openalex-snapshot
ME-TCAM: Memory-Efficient Ternary Content Addressable Memory Based on Multipumping-Enabled LUTRAM on FPGA
inferred← citeshttps://doi.org/10.1109/sibircon56155.2022.10016993openalex-snapshot
Network Interface Module Development on Heterogeneous Computing System
inferred← citeshttps://doi.org/10.1109/tvlsi.2020.3026840openalex-snapshot
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs
inferred← citeshttps://doi.org/10.1155/2021/5544435openalex-snapshot
PackeX: Low‐Power High‐Performance Packet Classifier Using Memory on FPGAs
inferred← citeshttps://doi.org/10.11591/ijeecs.v22.i1.pp89-96openalex-snapshot
Algorithmic TCAM on FPGA with data collision approach
inferred← citeshttps://doi.org/10.33180/infmidem2022.304openalex-snapshot
Energy Efficient and Low dynamic power Consumption TCAM on FPGA
inferred← citeshttps://doi.org/10.4218/etrij.2023-0206openalex-snapshot
High‐speed and reduced energy delay product TCAM on FPGA for network routers
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