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EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

https://doi.org/10.3390/electronics7090186

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s00034-014-9796-3openalex-snapshot

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

inferredcites →https://doi.org/10.1016/j.vlsi.2007.11.003openalex-snapshot

High performance set associative translation lookaside buffers for low power microprocessors

inferredcites →https://doi.org/10.1109/12.888055openalex-snapshot

A low-power CAM design for LZ data compression

inferredcites →https://doi.org/10.1109/4.974545openalex-snapshot

A power-efficient wide-range phase-locked loop

inferredcites →https://doi.org/10.1109/40.903060openalex-snapshot

Fast updating algorithms for TCAM

inferredcites →https://doi.org/10.1109/access.2018.2816039openalex-snapshot

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation

inferredcites →https://doi.org/10.1109/access.2018.2822311openalex-snapshot

Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA

inferredcites →https://doi.org/10.1109/access.2018.2854306openalex-snapshot

Fast Pattern Recognition Through an LBP Driven CAM on FPGA

inferredcites →https://doi.org/10.1109/ancs.2013.6665177openalex-snapshot

Scalable Ternary Content Addressable Memory implementation using FPGAs

inferredcites →https://doi.org/10.1109/hotchips.2009.7478379openalex-snapshot

Xilinx Virtex-6 and Spartan-6 FPGA families

inferredcites →https://doi.org/10.1109/ipdps.2008.4536259openalex-snapshot

Parallel IP lookup using multiple SRAM-based pipelines

inferredcites →https://doi.org/10.1109/ispass.2006.1620796openalex-snapshot

Modeling TCAM power for next generation network devices

inferredcites →https://doi.org/10.1109/ispass.2007.363753openalex-snapshot

CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications

inferredcites →https://doi.org/10.1109/jetcas.2016.2528638openalex-snapshot

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification

inferredcites →https://doi.org/10.1109/jproc.2015.2434888openalex-snapshot

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

inferredcites →https://doi.org/10.1109/jssc.2017.2681458openalex-snapshot

A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing

inferredcites →https://doi.org/10.1109/les.2017.2770225openalex-snapshot

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA

inferredcites →https://doi.org/10.1109/reconfig.2014.7032536openalex-snapshot

Low power RAM-based hierarchical CAM on FPGA

inferredcites →https://doi.org/10.1109/tc.2004.108openalex-snapshot

CoPTUA: Consistent Policy Table Update Algorithm for TCAM without locking

inferredcites →https://doi.org/10.1109/tcsi.2012.2215736openalex-snapshot

Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory

inferredcites →https://doi.org/10.1109/tencon.2015.7372837openalex-snapshot

UE-TCAM: An ultra efficient SRAM-based TCAM

inferredcites →https://doi.org/10.1109/tvlsi.2006.871760openalex-snapshot

A nonredundant ternary CAM circuit for network search engines

inferredcites →https://doi.org/10.1109/tvlsi.2014.2309350openalex-snapshot

Z-TCAM: An SRAM-based Architecture for TCAM

inferredcites →https://doi.org/10.1109/tvlsi.2016.2624990openalex-snapshot

Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology

inferredcites →https://doi.org/10.1109/tvlsi.2016.2636294openalex-snapshot

Resource-Efficient SRAM-Based Ternary Content Addressable Memory

inferredcites →https://doi.org/10.1145/1108956.1108958openalex-snapshot

Survey and taxonomy of packet classification techniques

inferredcites →https://doi.org/10.1145/1508128.1508162openalex-snapshot

Large-scale wire-speed packet classification on FPGAs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-17551-0_29openalex-snapshot

Multi-region SRAM-Based TCAM for Longest Prefix

inferred← citeshttps://doi.org/10.1007/s11227-023-05357-2openalex-snapshot

Using FPGA-based content-addressable memory for mnemonics instruction searching in assembler design

inferred← citeshttps://doi.org/10.1016/j.asej.2023.102478openalex-snapshot

A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

inferred← citeshttps://doi.org/10.1016/j.dcan.2022.04.010openalex-snapshot

Efficient pipelined flow classification for intelligent data processing in IoT

inferred← citeshttps://doi.org/10.1016/j.future.2021.09.037openalex-snapshot

Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey

inferred← citeshttps://doi.org/10.1016/j.phycom.2022.101677openalex-snapshot

An efficient packet parser architecture for software-defined 5G networks

inferred← citeshttps://doi.org/10.1063/5.0176561openalex-snapshot

Multibit soft error resilient SRAM based TCAM for FPGA

inferred← citeshttps://doi.org/10.1109/access.2021.3138399openalex-snapshot

EFS: Efficient Storage Optimization for Multistage Flow-Table in Software-Defined Satellite Network

inferred← citeshttps://doi.org/10.1109/csnt51715.2021.9509600openalex-snapshot

Energy-Efficient Design of RAM and Its Implementation on FPGA

inferred← citeshttps://doi.org/10.1109/icaect60202.2024.10468979openalex-snapshot

FPGA Architecture for High-speed TCAM-based Packet Parsing

inferred← citeshttps://doi.org/10.1109/icjece.2020.3025198openalex-snapshot

Fast Mapping and Updating Algorithms for a Binary CAM on FPGA

inferred← citeshttps://doi.org/10.1109/les.2019.2956154openalex-snapshot

High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA

inferred← citeshttps://doi.org/10.1109/siu49456.2020.9302072openalex-snapshot

A Hardware Accelerated Packet Classifier Design for A Network Router

inferred← citeshttps://doi.org/10.1109/tvlsi.2020.2993168openalex-snapshot

RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs

inferred← citeshttps://doi.org/10.1109/tvlsi.2020.3026840openalex-snapshot

FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs

inferred← citeshttps://doi.org/10.1155/2021/5544435openalex-snapshot

PackeX: Low‐Power High‐Performance Packet Classifier Using Memory on FPGAs

inferred← citeshttps://doi.org/10.11591/ijeecs.v22.i1.pp89-96openalex-snapshot

Algorithmic TCAM on FPGA with data collision approach

inferred← citeshttps://doi.org/10.21058/gjecs.2020.51005openalex-snapshot

LVCMOS Based Design OF Energy Efficient RAM On FPGA

inferred← citeshttps://doi.org/10.26634/jcir.8.2.18087openalex-snapshot

Simulation Of Cascaded Gate-Based Ternary Content-Addressable Memory

inferred← citeshttps://doi.org/10.33180/infmidem2022.304openalex-snapshot

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

inferred← citeshttps://doi.org/10.3390/electronics8050584openalex-snapshot

Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

inferred← citeshttps://doi.org/10.3390/electronics9020353openalex-snapshot

BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs

inferred← citeshttps://doi.org/10.35940/ijeat.a1083.1291s319openalex-snapshot

Low Power Implementation Of Ternary Content Addressable Memory (TCAM)

inferred← citeshttps://doi.org/10.5772/intechopen.104072openalex-snapshot

Computer Memory and Data Storage

inferred← citeshttps://doi.org/10.5772/intechopen.112060openalex-snapshot

New Content Addressable Memory Architecture for Multi-Core Applications

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