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Executing behavioural definitions in higher order logic

https://doi.org/10.48456/tr-140
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Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44957-4_36openalex-snapshot
Representing Object Code
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_128openalex-snapshot
A functional approach for formalizing regular hardware structures
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_136openalex-snapshot
Linking Higher Order Logic to a VLSI CAD system
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_149openalex-snapshot
Modelling bit vectors in HOL: The word library
inferred← citeshttps://doi.org/10.1007/3-540-57826-9_158openalex-snapshot
From abstract data types to shift registers:
inferred← citeshttps://doi.org/10.1007/3-540-58450-1_38openalex-snapshot
Symbolic animation as a proof tool
inferred← citeshttps://doi.org/10.1007/3-540-60045-0_38openalex-snapshot
Hardware verification using monadic second-order logic
inferred← citeshttps://doi.org/10.1016/0165-6074(88)90081-6openalex-snapshot
Formal specification and verification of microprocessor systems
inferred← citeshttps://doi.org/10.1016/0167-9260(89)90004-7openalex-snapshot
Formal specification and verification of microprocessor systems
inferred← citeshttps://doi.org/10.1016/b978-0-444-89880-7.50039-5openalex-snapshot
Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic
inferred← citeshttps://doi.org/10.1109/dac.1988.14758openalex-snapshot
Formal specification and verification of hardware: a comparative case study
inferred← citeshttps://doi.org/10.1109/hol.1991.596292openalex-snapshot
A Verified Compiler For A Structured Assembly Language
inferred← citeshttps://doi.org/10.48456/tr-201openalex-snapshot
Formalizing abstraction mechanisms for hardware verification in higher order logic
inferred← citeshttps://doi.org/10.7146/brics.v2i7.19509openalex-snapshot
Hardware Verification using Monadic Second-Order Logic
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