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Formalizing abstraction mechanisms for hardware verification in higher order logic

https://doi.org/10.48456/tr-201
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Formal Verification and Implementation of a Microprocessor
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Towards a framework for dealing with system timing in Very High Level Silicon Compilers
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Abstraction Mechanisms for Hardware Verification
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HARDWARE VERIFICATION BY FORMAL PROOF
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PROVING A COMPUTER CORRECT IN HIGHER ORDER LOGIC
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SPECIFICATION AND VLSI DESIGN
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A formulation of the simple theory of types
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Executing behavioural definitions in higher order logic
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Formalising an integrated circuit design style in higher order logic
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LCF_LSM, A system for specifying and verifying hardware
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HOL A machine oriented formulation of higher order logic
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Formal Design Verification of Digital Systems

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Abstraction techniques for modeling real-world interface chips
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Modelling bit vectors in HOL: The word library
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A mechanisation of name-carrying syntax up to alpha-conversion
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Datatypes in L2
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Using higher order logic for modelling real-time protocols
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Formal Hardware Verification Methods: A Survey
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Formal hardware verification methods: A survey
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A methodology for efficient hardware verification
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Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications
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Deduction as an Engineering Science
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Annotated reasoning
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An Engineering Methodology for the Formal Verification of Function Block Based Systems
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