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The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors

https://doi.org/10.5555/645989.674321
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-3604-8_9openalex-snapshot
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes*
inferredcites →https://doi.org/10.1016/s1383-7621(00)00007-2openalex-snapshot
An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/12.256449openalex-snapshot
Cache invalidation patterns in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/12.752663openalex-snapshot
The impact of exploiting instruction-level parallelism on shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/2.707614openalex-snapshot
Multiprocessors should support simple memory consistency models
inferredcites →https://doi.org/10.1109/2.982915openalex-snapshot
Rsim: simulating shared-memory multiprocessors with ILP processors
inferredcites →https://doi.org/10.1109/40.653032openalex-snapshot
Starfire: extending the SMP envelope
inferredcites →https://doi.org/10.1109/hpca.1999.744359openalex-snapshot
Improving CC-NUMA performance using Instruction-based Prediction
inferredcites →https://doi.org/10.1109/hpca.2000.824346openalex-snapshot
High-throughput coherence controllers
inferredcites →https://doi.org/10.1109/hpca.2000.824347openalex-snapshot
Coherence communication prediction in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2001.903255openalex-snapshot
A new scalable directory architecture for large-scale multiprocessors
inferredcites →https://doi.org/10.1109/icpp.1996.537154openalex-snapshot
Reducing cache invalidation overheads in wormhole routed DSMs using multidestination message passing
inferredcites →https://doi.org/10.1109/ipdps.2000.846053openalex-snapshot
Reducing ownership overhead for load-store sequences in cache-coherent multiprocessors
inferredcites →https://doi.org/10.1109/ipdps.2002.1015554openalex-snapshot
A. novel approach to reduce L2 miss latency in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/pccc.2000.830368openalex-snapshot
A novel multicast scheme to reduce cache invalidation overheads in DSM systems
inferredcites →https://doi.org/10.1109/spdp.1996.570332openalex-snapshot
An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/130823.130824openalex-snapshot
SPLASH
inferredcites →https://doi.org/10.1145/223982.223990openalex-snapshot
The SPLASH-2 programs
inferredcites →https://doi.org/10.1145/223982.223995openalex-snapshot
Dynamic self-invalidation
inferredcites →https://doi.org/10.1145/263580.263599openalex-snapshot
Eliminating cache conflict misses through XOR-based placement functions
inferredcites →https://doi.org/10.1145/264107.264206openalex-snapshot
The SGI Origin
inferredcites →https://doi.org/10.1145/279358.279386openalex-snapshot
Using prediction to accelerate coherence protocols
inferredcites →https://doi.org/10.1145/300979.300994openalex-snapshot
Memory sharing predictor: the key to a speculative coherent DSM
inferredcites →https://doi.org/10.1145/300979.301004openalex-snapshot
Multicast snooping: a new coherence method using a multicast address network
inferredcites →https://doi.org/10.1145/325096.325130openalex-snapshot
An empirical evaluation of two memory-efficient directory methods
inferredcites →https://doi.org/10.1145/339647.339669openalex-snapshot
Selective, accurate, and timely self-invalidation using last-touch prediction
inferredcites →https://doi.org/10.1145/356989.356991openalex-snapshot
Architecture and design of AlphaServer GS320

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-540-77220-0_17openalex-snapshot
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-11802-9_24openalex-snapshot
Write Invalidation Analysis in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/s00521-012-1267-9openalex-snapshot
Predicting the performance measures of a message-passing multiprocessor architecture using artificial neural networks
inferred← citeshttps://doi.org/10.1007/s10766-013-0247-8openalex-snapshot
Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2009.06.003openalex-snapshot
Performance evaluation of directory protocols on an optical broadcast-based distributed shared memory multiprocessor
inferred← citeshttps://doi.org/10.1016/j.eswa.2009.09.042openalex-snapshot
Application of self organizing maps for investigating network latency on a broadcast-based distributed shared memory multiprocessor
inferred← citeshttps://doi.org/10.1016/j.eswa.2010.02.092openalex-snapshot
Predicting the performance measures of an optical distributed shared memory multiprocessor by using support vector regression
inferred← citeshttps://doi.org/10.1016/j.sysarc.2007.09.005openalex-snapshot
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
inferred← citeshttps://doi.org/10.1109/hpca.2007.346210openalex-snapshot
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
inferred← citeshttps://doi.org/10.1109/ipdps.2004.1302914openalex-snapshot
A scalable architecture for distributed shared memory multiprocessors using optical interconnects
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370533openalex-snapshot
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536258openalex-snapshot
An interconnect-aware power efficient cache coherence protocol for CMPs
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536287openalex-snapshot
DiCo-CMP: Efficient cache coherency in tiled CMP architectures
inferred← citeshttps://doi.org/10.1109/jlt.2004.833249openalex-snapshot
RAPID: Reconfigurable and Scalable All-Photonic Interconnect for Distributed Shared Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/micro.2008.4771778openalex-snapshot
Token tenure: PATCHing token counting using directory-based cache coherence
inferred← citeshttps://doi.org/10.1109/micro.2012.40openalex-snapshot
Predicting Coherence Communication by Tracking Synchronization Points at Run Time
inferred← citeshttps://doi.org/10.1109/mm.2005.7openalex-snapshot
Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/pact52795.2021.00024openalex-snapshot
Invalidate or Update? Revisiting Coherence for Tomorrow's Cache Hierarchies
inferred← citeshttps://doi.org/10.1109/tpds.2010.43openalex-snapshot
A Direct Coherence Protocol for Many-Core Chip Multiprocessors
inferred← citeshttps://doi.org/10.1145/1128022.1128065openalex-snapshot
An efficient cache design for scalable glueless shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/1150019.1136515openalex-snapshot
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1145/1242531.1242568openalex-snapshot
Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols
inferred← citeshttps://doi.org/10.1145/1839667.1839668openalex-snapshot
Token tenure and PATCH
inferred← citeshttps://doi.org/10.1145/1854273.1854331openalex-snapshot
SWEL
inferred← citeshttps://doi.org/10.1145/1882453.1882458openalex-snapshot
An adaptive cache coherence protocol for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1995896.1995941openalex-snapshot
A composite and scalable cache coherence protocol for large scale CMPs
inferred← citeshttps://doi.org/10.1145/2611756openalex-snapshot
Integrated Coherence Prediction
inferred← citeshttps://doi.org/10.1145/2807591.2807649openalex-snapshot
Automatic sharing classification and timely push for cache-coherent systems
inferred← citeshttps://doi.org/10.1145/859618.859640openalex-snapshot
Token coherence
inferred← citeshttps://doi.org/10.1145/859618.859642openalex-snapshot
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/871656.859640openalex-snapshot
Token coherence
inferred← citeshttps://doi.org/10.1145/871656.859642openalex-snapshot
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.4995/thesis/10251/6024openalex-snapshot
Efficient techniques to provide scalability for token-based cache coherence protocols.
inferred← citeshttps://doi.org/10.5772/9454openalex-snapshot
Cache Coherence Protocols for Many-Core CMPs
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