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Cache Coherence Protocols for Many-Core CMPs

https://doi.org/10.5772/9454
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-3604-8_9openalex-snapshot
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes*
inferredcites →https://doi.org/10.1007/978-3-540-71528-3_2openalex-snapshot
High-Performance Embedded Architecture and Compilation Roadmap
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/40.768506openalex-snapshot
UltraSPARC-III: designing third-generation 64-bit performance
inferredcites →https://doi.org/10.1109/5.920580openalex-snapshot
The future of wires
inferredcites →https://doi.org/10.1109/empdp.2002.994207openalex-snapshot
SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor systems
inferredcites →https://doi.org/10.1109/hpca.2001.903255openalex-snapshot
A new scalable directory architecture for large-scale multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2005.17openalex-snapshot
Improving Multiple-CMP Systems Using Token Coherence
inferredcites →https://doi.org/10.1109/hpca.2007.346210openalex-snapshot
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
inferredcites →https://doi.org/10.1109/hpca.2009.4798238openalex-snapshot
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
inferredcites →https://doi.org/10.1109/iiswc.2005.1525999openalex-snapshot
The ALPbench benchmark suite for complex multimedia applications
inferredcites →https://doi.org/10.1109/ipdps.2008.4536287openalex-snapshot
DiCo-CMP: Efficient cache coherency in tiled CMP architectures
inferredcites →https://doi.org/10.1109/isca.2000.854398openalex-snapshot
Piranha: a scalable architecture based on single-chip multiprocessing
inferredcites →https://doi.org/10.1109/isca.2003.1207001openalex-snapshot
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.2005.53openalex-snapshot
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
inferredcites →https://doi.org/10.1109/mcc.1999.766975openalex-snapshot
Parallel Computer Architecture: A Hardware/Software Approach
inferredcites →https://doi.org/10.1109/micro.2006.10openalex-snapshot
ASR: Adaptive Selective Replication for CMP Caches
inferredcites →https://doi.org/10.1109/micro.2008.4771777openalex-snapshot
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/mm.2006.8openalex-snapshot
Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays
inferredcites →https://doi.org/10.1109/pact.2002.1106014openalex-snapshot
The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors
inferredcites →https://doi.org/10.1145/106972.106995openalex-snapshot
LimitLESS directories
inferredcites →https://doi.org/10.1145/1080695.1069998openalex-snapshot
Victim Replication
inferredcites →https://doi.org/10.1145/1080695.1070004openalex-snapshot
Interconnections in Multi-Core Architectures
inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1454115.1454138openalex-snapshot
Improving support for locality and fine-grain sharing in chip multiprocessors
inferredcites →https://doi.org/10.1145/181181.181271openalex-snapshot
An evaluation of directory protocols for medium-scale shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/223982.223990openalex-snapshot
The SPLASH-2 programs
inferredcites →https://doi.org/10.1145/285930.285995openalex-snapshot
An evaluation of directory schemes for cache coherence
inferredcites →https://doi.org/10.1145/339647.339691openalex-snapshot
Clock rate versus IPC
inferredcites →https://doi.org/10.1145/339647.339696openalex-snapshot
Piranha
inferredcites →https://doi.org/10.1145/342001.339691openalex-snapshot
Clock rate versus IPC
inferredcites →https://doi.org/10.1145/356989.356992openalex-snapshot
Timestamp snooping
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/605418.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/859618.859640openalex-snapshot
Token coherence
inferredcites →https://doi.org/10.1145/859618.859642openalex-snapshot
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/966747.966750openalex-snapshot
Interconnect-power dissipation in a microprocessor
inferredcites →https://doi.org/10.1145/966748.966750openalex-snapshot
Interconnect-power dissipation in a microprocessor
inferredcites →https://doi.org/10.1147/rd.516.0639openalex-snapshot
IBM POWER6 microarchitecture
inferredcites →https://doi.org/10.1535/itj.1103.01openalex-snapshot
Integration Challenges and Tradeoffs for Terascale Architectures
inferredcites →https://doi.org/10.21236/ada237629openalex-snapshot
LimitLESS Directories: A Scalable Cache Coherence Scheme
inferredcites →https://doi.org/10.5555/645989.674321openalex-snapshot
The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-642-35898-2_6openalex-snapshot
Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor
inferred← citeshttps://doi.org/10.1109/access.2023.3234933openalex-snapshot
NCDE: In-Network Caching for Directory Entries to Expedite Data Access in Tiled-Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/iccsnt.2015.7490872openalex-snapshot
A load-aware broadcast scheme supporting rectangular regions for many-core processors
inferred← citeshttps://doi.org/10.1109/iceiec.2016.7589749openalex-snapshot
A low cost design of hardware support for on-chip message passing in manycore processors
inferred← citeshttps://doi.org/10.1109/icisce.2016.34openalex-snapshot
A Subnetting Mechanism with Low Cost Deadlock-Free Design for Irregular Topologies in NoC-based Manycore Processors
inferred← citeshttps://doi.org/10.1109/imcec.2016.7867239openalex-snapshot
Reconfigurable MPB combined with cache coherence protocol in many-core
inferred← citeshttps://doi.org/10.1109/isvlsi.2015.35openalex-snapshot
RWT: Suppressing Write-Through Cost When Coherence is Not Needed
inferred← citeshttps://doi.org/10.1109/isvlsi.2017.25openalex-snapshot
Decoupling Translation Lookaside Buffer Coherence from Cache Coherence
inferred← citeshttps://doi.org/10.1109/sc.2012.61openalex-snapshot
Hardware-software coherence protocol for the coexistence of caches and local memories
inferred← citeshttps://doi.org/10.1109/tc.2013.194openalex-snapshot
Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories
inferred← citeshttps://doi.org/10.1145/2749469.2750411openalex-snapshot
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
inferred← citeshttps://doi.org/10.1145/2786572.2788710openalex-snapshot
Networking Challenges and Prospective Impact of Broadcast-Oriented Wireless Networks-on-Chip
inferred← citeshttps://doi.org/10.17016/feds.2017.005openalex-snapshot
How Fast are Semiconductor Prices Falling?
inferred← citeshttps://doi.org/10.5555/2388996.2389117openalex-snapshot
Hardware-software coherence protocol for the coexistence of caches and local memories
inferred← citeshttps://doi.org/10.5821/dissertation-2117-105575openalex-snapshot
Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94621openalex-snapshot
Software caching techniques and hardware optimizations for on-chip local memories
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