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Integrating adaptive on-chip storage structures for reduced dynamic power

https://doi.org/10.5555/645989.674326
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot
The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/40.782564openalex-snapshot
Design challenges of technology scaling
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An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches
inferredcites →https://doi.org/10.1109/iccd.1998.727028openalex-snapshot
The Alpha 21264 microprocessor architecture
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The non-critical buffer: using load latency tolerance to improve data cache efficiency
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Load latency tolerance in dynamically scheduled processors
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Static energy reduction techniques for microprocessor caches
inferredcites →https://doi.org/10.1145/339647.339657openalex-snapshot
Wattch
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Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
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A circuit level implementation of an adaptive issue queue for power-aware microprocessors
inferredcites →https://doi.org/10.1145/379240.379266openalex-snapshot
Energy-effective issue logic
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Cache decay
inferredcites →https://doi.org/10.1145/545214.545232openalex-snapshot
Drowsy caches
inferredcites →https://doi.org/10.1145/545214.545241openalex-snapshot
Managing multi-configuration hardware via dynamic working set analysis
inferredcites →https://doi.org/10.1147/rd.461.0005openalex-snapshot
POWER4 system microarchitecture
inferredcites →https://doi.org/10.5555/255235.255288openalex-snapshot
Register renaming and dynamic speculation: an alternative approach
inferredcites →https://doi.org/10.5555/320080.320119openalex-snapshot
Selective cache ways: on-demand cache resource allocation
inferredcites →https://doi.org/10.5555/563998.564007openalex-snapshot
Reducing set-associative cache energy via way-prediction and selective direct-mapping
inferredcites →https://doi.org/10.5555/563998.564011openalex-snapshot
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Offline Phase Analysis and Optimization for Multi-configuration Processors
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Performance and Power Evaluation of an Intelligently Adaptive Data Cache
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ERA – Embedded Reconfigurable Architectures
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Computer Architecture Techniques for Power-Efficiency
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Multi-Core Cache Hierarchies
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Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
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Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols
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Multi-cache resizing via greedy coordinate descent
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An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking
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A phase adaptive cache hierarchy for SMT processors
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A survey of architectural techniques for improving cache power efficiency
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Exploiting program phase behavior for energy reduction on multi-configuration processors
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An Analysis of Program Phase Behavior and its Predictability
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OS-aware Tuning: Improving Instruction Cache Energy Efficiency on System Workloads
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Dynamic Split: Flexible Border Between Instruction and Data Cache
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Leveraging Data Promotion for Low Power D-NUCA Caches
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Adaptive Cache Memories for SMT Processors
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Front-end policies for improved issue efficiency in SMT processors
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The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
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Transition Phase Classification and Prediction
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Energy-efficient address translation
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Impact of Partitioning Cache Schemes on the Cache Hierarchy of SMT Processors
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Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-based Scheduling
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Scheduler Optimization by Exploring Wakeup Locality
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Partial tag comparison: a new technology for power-efficient set-associative cache designs
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Configurable platforms with dynamic platform management: an efficient alternative to application-specific system-on-chips
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Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy
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Balancing Performance and Reliability in the Memory Hierarchy
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AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores
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Dynamically tuning processor resources with adaptive processing
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Dynamically Trading Frequency for Complexity in a GALS Microprocessor
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EVAL: Utilizing processors with variation-induced timing errors
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Reconfigurable energy efficient near threshold cache architectures
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A Predictive Model for Dynamic Microarchitectural Adaptivity Control
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Power- and complexity-aware issue queue designs
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Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors
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A dynamically tunable memory hierarchy
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Dynamic resizing of superscalar datapath components for energy efficiency
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Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality
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Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors
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Reducing Data Cache Susceptibility to Soft Errors
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Exploring Heterogeneity within a Core for Improved Power Efficiency
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A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior
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MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration
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Way Sharing Set Associative Cache Architecture
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Location cache
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A Formal Approach to Frequent Energy Adaptations for Multimedia Applications
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IATAC: a smart predictor to turn-off L2 cache lines
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A highly configurable cache for low energy embedded systems
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Locality analysis to control dynamically way-adaptable caches
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Power reduction techniques for microprocessor systems
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Cache size selection for performance, energy and reliability of time-constrained systems
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Wavelet-based phase classification
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Heterogeneous way-size cache
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Effective management of multiple configurable units using dynamic optimization
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Cross-component energy management
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Improving power efficiency of D-NUCA caches
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Improving SMT performance
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Reducing peak power with a table-driven adaptive processor core
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Power and performance aware reconfigurable cache for CMPs
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ADAM
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PEPON
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Reuse-based online models for caches
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A survey on cache tuning from a power/energy perspective
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Flicker
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Reuse-based online models for caches
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Flicker
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Virtually split cache
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Dynamic microarchitectural adaptation using machine learning
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On Detecting and Using Memory Phases in Multimedia Systems
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Using multiple input, multiple output formal control to maximize resource efficiency in architectures
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Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors
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Joint local and global hardware adaptations for energy
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Joint local and global hardware adaptations for energy
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Joint local and global hardware adaptations for energy
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Joint local and global hardware adaptations for energy
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Predictive dynamic thermal management for multimedia applications
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A highly configurable cache architecture for embedded systems
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Energy efficient co-adaptive instruction fetch and issue
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Positional adaptation of processors
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Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving
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Energy efficient co-adaptive instruction fetch and issue
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Positional adaptation of processors
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Way adaptable D-NUCA caches
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Computer Architecture Techniques for Power-Efficiency
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Dynamic cache reconfiguration based techniques for improving cache energy efficiency
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Energy savings in simultaneous multi-threaded processors through dynamic resizing of datapath resources
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Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors
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Program phase detection and exploitation
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Dynamic voltage and cache reconfiguration for low power
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ADACORE: Achieving Energy Efficiency via Adaptive Core Morphing at Runtime
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