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Dynamically Trading Frequency for Complexity in a GALS Microprocessor
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44572-2_6openalex-snapshot
Compiler-Directed Dynamic Frequency and Voltage Scheduling
inferredcites →https://doi.org/10.1007/978-1-4020-5869-1_14openalex-snapshot
Compiler-Directed Dynamic CPU Frequency and Voltage Scaling
inferredcites →https://doi.org/10.1109/12.102825openalex-snapshot
Pipeline design tradeoffs in a 32-bit gallium arsenide microprocessor
inferredcites →https://doi.org/10.1109/4.509850openalex-snapshot
CACTI: an enhanced cache access and cycle time model
inferredcites →https://doi.org/10.1109/54.825676openalex-snapshot
Runtime reconfiguration techniques for efficient general-purpose computation
inferredcites →https://doi.org/10.1109/arvlsi.1997.634845openalex-snapshot
Interfacing synchronous and asynchronous modules within a high-speed pipeline
inferredcites →https://doi.org/10.1109/asic.1999.806526openalex-snapshot
Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems
inferredcites →https://doi.org/10.1109/async.2004.1299297openalex-snapshot
Hiding synchronization delays in a GALS processor microarchitecture
inferredcites →https://doi.org/10.1109/hpca.2002.995696openalex-snapshot
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
inferredcites →https://doi.org/10.1109/isca.1998.694788openalex-snapshot
Dynamic IPC/clock rate optimization
inferredcites →https://doi.org/10.1109/isca.2002.1003557openalex-snapshot
The optimum pipeline depth for a microprocessor
inferredcites →https://doi.org/10.1109/isca.2002.1003559openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1109/isca.2002.1003573openalex-snapshot
Power and performance evaluation of globally asynchronous locally synchronous processors
inferredcites →https://doi.org/10.1109/isca.2002.1003581openalex-snapshot
Managing multi-configuration hardware via dynamic working set analysis
inferredcites →https://doi.org/10.1109/micro.2001.991105openalex-snapshot
Reducing set-associative cache energy via way-prediction and selective direct-mapping
inferredcites →https://doi.org/10.1109/micro.2001.991108openalex-snapshot
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
inferredcites →https://doi.org/10.1109/micro.2002.1176263openalex-snapshot
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
inferredcites →https://doi.org/10.1109/pact.2002.1106013openalex-snapshot
Integrating adaptive on-chip storage structures for reduced dynamic power
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/279358.279397openalex-snapshot
Dynamic IPC/clock rate optimization
inferredcites →https://doi.org/10.1145/360128.360153openalex-snapshot
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
inferredcites →https://doi.org/10.1145/368122.368807openalex-snapshot
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
inferredcites →https://doi.org/10.1145/545214.545217openalex-snapshot
The optimum pipeline depth for a microprocessor
inferredcites →https://doi.org/10.1145/545214.545219openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1145/545214.545233openalex-snapshot
Power and performance evaluation of globally asynchronous locally synchronous processors
inferredcites →https://doi.org/10.1145/545214.545241openalex-snapshot
Managing multi-configuration hardware via dynamic working set analysis
inferredcites →https://doi.org/10.1145/605397.605413openalex-snapshot
Joint local and global hardware adaptations for energy
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/859618.859621openalex-snapshot
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
inferredcites →https://doi.org/10.1145/871656.859621openalex-snapshot
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
inferredcites →https://doi.org/10.5555/563998.564007openalex-snapshot
Reducing set-associative cache energy via way-prediction and selective direct-mapping
inferredcites →https://doi.org/10.5555/563998.564011openalex-snapshot
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
inferredcites →https://doi.org/10.5555/645989.674326openalex-snapshot
Integrating adaptive on-chip storage structures for reduced dynamic power
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-540-69338-3_10openalex-snapshot
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
inferred← citeshttps://doi.org/10.1016/j.micpro.2011.08.008openalex-snapshot
A phase adaptive cache hierarchy for SMT processors
inferred← citeshttps://doi.org/10.1109/dsd.2010.69openalex-snapshot
Adaptive Cache Memories for SMT Processors
inferred← citeshttps://doi.org/10.1109/hpca.2007.346183openalex-snapshot
Implications of Device Timing Variability on Full Chip Timing
inferred← citeshttps://doi.org/10.1109/igcc.2013.6604475openalex-snapshot
Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy
inferred← citeshttps://doi.org/10.1109/pact.2009.44openalex-snapshot
Core-Selectability in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2012.6379024openalex-snapshot
A physical design study of fabscalar-generated superscalar cores
inferred← citeshttps://doi.org/10.1145/1108956.1108957openalex-snapshot
Power reduction techniques for microprocessor systems
inferred← citeshttps://doi.org/10.1145/1187976.1187981openalex-snapshot
Effective management of multiple configurable units using dynamic optimization
inferred← citeshttps://doi.org/10.1145/1353629.1353644openalex-snapshot
Implications of device timing variability on full chip timing
inferred← citeshttps://doi.org/10.1145/1555754.1555763openalex-snapshot
Dynamic MIPS rate stabilization in out-of-order processors
inferred← citeshttps://doi.org/10.1145/1555815.1555763openalex-snapshot
Dynamic MIPS rate stabilization in out-of-order processors
inferred← citeshttps://doi.org/10.1145/2714575openalex-snapshot
Dynamic MIPS Rate Stabilization for Complex Processors
inferred← citeshttps://doi.org/10.5555/1999416.1999421openalex-snapshot
Simulating a LAGS processor to consider variable latency on L1 D-Cache
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95043openalex-snapshot
Design of a distributed memory unit for clustered microarchitectures
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