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VLSI

https://doi.org/10.5772/139
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inferred← citeshttps://doi.org/10.1109/asscc.2013.6691069openalex-snapshot
209mW 11Gbps 130GHz CMOS transceiver for indoor wireless communication
inferred← citeshttps://doi.org/10.1109/cicc60959.2024.10528980openalex-snapshot
A 4.2pJ/Pixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-Path Aggregation Semi-Global Matching
inferred← citeshttps://doi.org/10.1109/cicc60959.2024.10528988openalex-snapshot
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering
inferred← citeshttps://doi.org/10.1109/cicc60959.2024.10529052openalex-snapshot
A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUT Augmentation
inferred← citeshttps://doi.org/10.1109/cstic64481.2025.11017821openalex-snapshot
Ferroelectric Materials, Devices and Chip Technologies for Enhanced Computational and Storage Capabilities
inferred← citeshttps://doi.org/10.1109/drc66027.2025.11105752openalex-snapshot
Oxide Semiconductors TFTs Integration in CMOS BEOL: Device Considerations for Enabling Novel Applications
inferred← citeshttps://doi.org/10.1109/drc66027.2025.11105756openalex-snapshot
20-50 nm Channel Length Single-Gate a-IGZO TFTs with Superior Gate Control and Reduced Short-Channel Effects
inferred← citeshttps://doi.org/10.1109/edtm58488.2024.10511325openalex-snapshot
Erase Efficiency Improvement of Ferroelectric FET with IGZO Channel by P-Type SnOx Layer
inferred← citeshttps://doi.org/10.1109/edtm58488.2024.10511418openalex-snapshot
GAA Technology Innovations for 2nm Logic node and Beyond
inferred← citeshttps://doi.org/10.1109/edtm58488.2024.10511775openalex-snapshot
Compensation of Conductance Mismatch with Redundant Bit-lines for RRAM-based Voltage Sensing Mode Computing-in-Memory
inferred← citeshttps://doi.org/10.1109/edtm58488.2024.10511791openalex-snapshot
Physics-based Scalable Compact Model for Terminal Charge, Intrinsic Capacitance and Drain Current in Nanosheet FETs
inferred← citeshttps://doi.org/10.1109/edtm58488.2024.10512230openalex-snapshot
Dissecting Parasitic Capacitance in Nanosheet FETs: An Analytical Perspective
inferred← citeshttps://doi.org/10.1109/edtm61175.2025.11040216openalex-snapshot
Characteristic Length of Transition-Metal Dichalcogenides Based Complementary Field-Effect Transistors
inferred← citeshttps://doi.org/10.1109/edtm61175.2025.11040570openalex-snapshot
Achieving High Endurance Ferroelectricity in Hf0.5Zr0.5O2 Thin Films on Ge Substrate Through Helium Ion Doping Engineering
inferred← citeshttps://doi.org/10.1109/edtm61175.2025.11040615openalex-snapshot
Prediction of Endurance Characteristics in Si FeFET with Ferroelectric Hf0.5Zr0.5O2
inferred← citeshttps://doi.org/10.1109/edtm61175.2025.11040842openalex-snapshot
A Novel Superlattice HfO2-ZrO2 Ferroelectric Tunnel FET for Overall Improvement in Memory Window, EOT and Disturb Immunity
inferred← citeshttps://doi.org/10.1109/edtm65772.2026.11497120openalex-snapshot
Influences of Voltage Cycling on Variations in HfO 2 -based 3D Trench FeRAM
inferred← citeshttps://doi.org/10.1109/edtm65772.2026.11497313openalex-snapshot
Threshold Voltage Control Techniques for Advanced Nodes
inferred← citeshttps://doi.org/10.1109/edtm65772.2026.11497385openalex-snapshot
Novel Gate-injected Ferroelectric FET-based Differential Fully-analog Computing-in-memory with In-situ Charge-domain Activation for Energy-efficient LLMs
inferred← citeshttps://doi.org/10.1109/icta64028.2024.10860483openalex-snapshot
22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications
inferred← citeshttps://doi.org/10.1109/icta68203.2025.11329942openalex-snapshot
A Bootstrap-Based Wordline Driver for Leakage Suppression in High-Density STT-MRAM
inferred← citeshttps://doi.org/10.1109/icta68203.2025.11330104openalex-snapshot
Area-Efficient Voltage Driving Scheme for High Density STT-MRAM Enhanced Write Operations
inferred← citeshttps://doi.org/10.1109/iedm45741.2023.10413688openalex-snapshot
Negative-U Defect Passivation in Oxide-Semiconductor by Channel Defect Self-Compensation Effect to Achieve Low Bias Stress VTH Instability of Low-Thermal Budget IGZO TFT and FeFETs
inferred← citeshttps://doi.org/10.1109/iedm45741.2023.10413857openalex-snapshot
Hybrid FeRAM/RRAM Synaptic Circuit Enabling On-Chip Inference and Learning at the Edge
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353484openalex-snapshot
Enhancement-mode BEOL In 2 O 3 FETs with Record Logic Performance: Experiments and Compact Modeling
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353534openalex-snapshot
Heterogeneous 3D Integrated RF Platform: III-V/III-N RF Blocks transfer onto CMOS via Die-to-Wafer Bonding Technology for High-Frequency and High-Density Wireless Communication Systems
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353543openalex-snapshot
Efficient Power Delivery Network of Enhancement and Depletion Mode GaN FeMHEMT by Ferroelectric Gate Stack for Voltage Regulators
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353553openalex-snapshot
A Novel Ferroelectric Charge-Steering Memcapacitor Array based Δ-CIM with Enhanced Parallelism and Self-Adaptive Sparsity for Edge LLMs
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353554openalex-snapshot
Imprint-centric Retention Loss in HfO 2 -based Ferroelectric Thin Films: Charge-assisted Defect Migration and Trap Neutralization Strategy
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353600openalex-snapshot
Highly Scaled FRAM Technology in 22FDX ® Achieving Sub 1 V Operation
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353608openalex-snapshot
First Demonstration of Quasi-Single-Crystal (QSC) HfZrON Gate Dielectric (κ=67) with sub-5 Å EOT and 4×10 -3 A/cm 2 J g for Si NSFET Scaling
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353624openalex-snapshot
First Demonstration of 2D Semiconductor Vertical pFET with Symmetrical Source/Drain Transport of I on >100 μA/μm with Extremely High thermal Stability up to 550 ℃ by Scalable Direct Channel Growth
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353630openalex-snapshot
Material Innovations and Solutions Enabling AI Architectures fueling the AI Era
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353642openalex-snapshot
Novel 3.3V RF-LDMOS in 16nm FinFET with the best RF and reliability trade-off enabling integrated Watt-level power amplifiers in connectivity SoC
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353675openalex-snapshot
Low V PGM Operation, Read Disturb, and Cell-to-Cell Interference in Scaled Vertical FeNAND
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353725openalex-snapshot
Trends in Embedded Volatile and Non-Volatile Memories for Scalable Edge AI Applications
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353734openalex-snapshot
Mechanics of Integration and Component Performance Step-up for Nanosheet Transistors with Ultrathin 2D Channel
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353753openalex-snapshot
First Demonstration of Three-Dimensional Thermal Conductivity Distribution Measurements of Interconnect Stacks Down to 3nm Process Nodes
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353794openalex-snapshot
First Demonstration of Monolayer WSe 2 p-FETs with 53 nm Ultra-scaled Pitch (L C =20 nm, L CH =33 nm, W=100 nm) and I on of 1195 μA/μm at V ds = -1 V
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353797openalex-snapshot
Ferroelectric Memcapacitor Crossbar Array with NAND Flash Structure for In-Memory Computing
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353816openalex-snapshot
High-Performance IGZO-based DrMOS with Vertical Channel Power Transistor for Monolithic 3D Integrated Active PDNs with On-Chip Voltage Conversion
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353820openalex-snapshot
First Demonstration of CFET Ring Oscillator and SRAM Bit-Cell Functionality at Gate Pitch Smaller Than 48 nm for Future Logic and SRAM Technology
inferred← citeshttps://doi.org/10.1109/iedm50572.2025.11353890openalex-snapshot
Crystal Indium Oxide for 64-kbit 2T0C Memory with 5-ns Read Time, Monolithically Stacked on Si CMOS
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10872988openalex-snapshot
Vertically Integrated Active Power Delivery Network (PDN) for Heterogenous 3D (H3D) Stacked Systems: 3D On-Chip Integration of GaN Power Devices on PDN with Direct Heat Spreading Layer Bonding
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873312openalex-snapshot
DRAM Technology & Design Optimization for Sub-10nm and Beyond
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873325openalex-snapshot
WNxCy VT Tuning of Split Gate Nanosheet CFETs with Dual Work Function Metals Achieving 0.93 VT Match/Improved 0.24V Noise Margin/Record Gain of 61V/V
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873334openalex-snapshot
First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873367openalex-snapshot
Silicon RibbonFET CMOS at 6nm Gate Length
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873397openalex-snapshot
Experimental Demonstration of Resonant Adiabatic Writing and Computing in Ferroelectric Capacitive Memory Array for Energy-Efficient Edge AI
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873412openalex-snapshot
High-Performance Monolayer-2D Stacked Nanosheet FETs with High ION~ 451 μA/μm and ION/IOFF > 109
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873418openalex-snapshot
ISO-Performance N-Type and P-Type MOSFETs on Densely Aligned CNT Array Enabled by Self-Aligned Extension Doping with Barrier Booster
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873421openalex-snapshot
Stacked Channel Transistors with 2D Materials: An Integration Perspective
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873426openalex-snapshot
Power and Thermal Integrity Analysis of High Performance and Low Power CPUs at Sub-2nm Node Designed with Various Advanced Backside PDNs
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873441openalex-snapshot
Enhancement-Mode Multichannel MoS2 Transistor with Spacer Engineering and Design-Technology Co-Optimization Based on the 8″ Platform
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873447openalex-snapshot
Comprehensive Performance Re-Assessment of Hafnia-Based Cross-Point FeRAM with Ultra-Fast and Low-Power Operation from Device/Array Perspective
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873464openalex-snapshot
Novel 4F2 Multi-Bit Dual-Gate 2T0C for High-Density DRAM with Improved Vertical-Channel IGZO TFTs by Self-Aligned Single-Step Process
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873480openalex-snapshot
Vertically Stackable Memcapacitor Crossbar Array Based on NAND Flash Array Structure
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873498openalex-snapshot
Ultra-Stacked Forksheet-FET and Monolithic Complementary-FET for Å7~5 node Visibility
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873499openalex-snapshot
First Demonstration of an N-P Oxide Semiconductor Complementary Gain Cell Memory
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873500openalex-snapshot
A Novel Channel-Less SOT-MRAM with 115% TMR, 2 ns Switching, and High Bit Yield (>99.9%)
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873503openalex-snapshot
Transfer Free 2D CMOS Multi Bridge Channel FET
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873511openalex-snapshot
Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873541openalex-snapshot
First Demonstration of BEOL Wafer-Scale All-ALD Channel CFETs Using IGZO and Te for Monolithic 3D Integration
inferred← citeshttps://doi.org/10.1109/iedm50854.2024.10873579openalex-snapshot
First Demonstration on the Transient Writing Characteristics of Multi-bit ALD IGZO 2T0C DRAM by Fast I-V Measurement
inferred← citeshttps://doi.org/10.1109/imw56887.2023.10145966openalex-snapshot
Comprehensive Study of Endurance Fatigue in the Scaled Si FeFET by in-situ Vth Measurement and Endurance Enhancement Strategy
inferred← citeshttps://doi.org/10.1109/imw61990.2025.11026976openalex-snapshot
Analog In-Memory-Compute with Multi-bit Silicon Ferro FinFET Array for Improved Energy and Area Efficiency
inferred← citeshttps://doi.org/10.1109/imw68301.2026.11532613openalex-snapshot
Quantitative Analysis of On-Current Discrepancy Between Monocrystalline Si and IGZO Channels in Stacked 3D-DRAM Transistors
inferred← citeshttps://doi.org/10.1109/imw68301.2026.11532617openalex-snapshot
Demonstration of 3D-Extendible, Logic-Compatible Sub-1.8 V Asymmetric Double-Gate FeFETs with Sub-3.5 nm Ultrathin HZO for Analog CIM
inferred← citeshttps://doi.org/10.1109/imw68301.2026.11532887openalex-snapshot
First Demonstration of Vertical Bit-Line 1T1C 3D DRAM Based-On Stacked Dual-Gate IGZO FETs with Excellent P/NBTS and High On-State Current
inferred← citeshttps://doi.org/10.1109/irps48228.2024.10529405openalex-snapshot
A New Clustering-Function-Based Formulation of Temporal and Spatial Clustering Model Involving Area Scaling and its Application to Parameter Extraction
inferred← citeshttps://doi.org/10.1109/isca.2014.6853194openalex-snapshot
A low power and reliable charge pump design for Phase Change Memories
inferred← citeshttps://doi.org/10.1109/isca.2016.63openalex-snapshot
Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures
inferred← citeshttps://doi.org/10.1109/jssc.2025.3616265openalex-snapshot
A 0.0035-mm 2 86-dB-SNR 1.25-MHz-BW Noise-Shaping SAR ADC Enabling kT/C Noise Shaping
inferred← citeshttps://doi.org/10.1109/micro.2012.10openalex-snapshot
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
inferred← citeshttps://doi.org/10.1109/ncc.2014.6811240openalex-snapshot
Optimal communication scheduling for iterative decoding of irregular codes
inferred← citeshttps://doi.org/10.1109/newcas.2012.6329077openalex-snapshot
Wireless transceivers for gigabit-per-second communications
inferred← citeshttps://doi.org/10.1109/snw63608.2024.10639201openalex-snapshot
Multi-Vt Gate Stack Technologies for Nanosheet and CFET Devices
inferred← citeshttps://doi.org/10.1109/snw63608.2024.10639205openalex-snapshot
BEOL-Compatible In2O3 Thin-Film Transistor with Linear Dielectric ZrO2 Achieving Dielectric Constant over 27 and Enhanced Field-Effect Mobility Up To 89.3 cm2·V−1·s−1
inferred← citeshttps://doi.org/10.1109/snw63608.2024.10639208openalex-snapshot
Enhanced Electrical Performance of Ultrathin Body Nanosheets
inferred← citeshttps://doi.org/10.1109/snw63608.2024.10639232openalex-snapshot
A Comparative Study of HBL and VBL 3D DRAM: Signal Margin, Bit-cell Density, and Scalability
inferred← citeshttps://doi.org/10.1109/snw63608.2024.10639242openalex-snapshot
Investigation of Sheet Width Dependence on Hot Carrier Degradation in GAA Nanosheet Transistors
inferred← citeshttps://doi.org/10.1109/vlsi-tsa.2013.6545584openalex-snapshot
Good memory performance and coexistence of bipolar and unipolar resistive switching for CMOS compatible Ti/HfOx/W memory
inferred← citeshttps://doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134110openalex-snapshot
BEOL Design and RF Performance of Stacked Si Nanosheets and Nanowires
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631312openalex-snapshot
On the Reliability of High-Performance Dual Gate (DG) W-Doped In 2 O 3 FET
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631314openalex-snapshot
A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631315openalex-snapshot
14nm FinFET Node Embedded MRAM Technology for Automotive Non-Volatile RAM Applications with Endurance Over 1E12-Cycles
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631320openalex-snapshot
Cell to Core-Periphery Overlap (C2O) Based on BCAT for Next Generation DRAM
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631321openalex-snapshot
A 96.4%-Efficiency Single-Duty-Cycled Buck-Boost Converter Achieving 1.9mV Ripple and 2.1mV Mode-Change Fluctuation for Mobile OLED Displays
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631324openalex-snapshot
Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631328openalex-snapshot
HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85°C
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631331openalex-snapshot
A 5.6µW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631340openalex-snapshot
Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631341openalex-snapshot
A 28nm Approximate / Binary 6T CAM for Sequence Alignment
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631347openalex-snapshot
A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631351openalex-snapshot
First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631359openalex-snapshot
A 6.78 MHz Wireless Power and Data Transfer System Achieving Simultaneous 52.6% End-to-End Efficiency and 4.0 Mb/s Forward Data Delivery with Interference-Free Rectifier
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631369openalex-snapshot
Positive Bias Stress Measurement Guideline and Band Analysis for Evaluating Instability of Oxide Semiconductor Transistors
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631375openalex-snapshot
NeRF-Navi: A 93.6-202.9µJ/task Switchable Approximate-Accurate NeRF Path Planning Processor with Dual Attention Engine and Outlier Bit-Offloading Core
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631387openalex-snapshot
Medusa: A 0.83/4.6 ${\mu}\mathrm{J}$/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631392openalex-snapshot
Expanding Design Technology Co-Optimization Potentials with Back-Side Interconnect Innovation
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631394openalex-snapshot
E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631398openalex-snapshot
Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631399openalex-snapshot
A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631401openalex-snapshot
On the Extreme Scaling of Transistors with Monolayer MOS2 Channel
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631403openalex-snapshot
A 7GHz High-Bandwidth 1R-1RW SRAM for Arm HPC Processor in 3nm Technology
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631407openalex-snapshot
A 5.8W, 0.00086% THD+N, 118dB PSRR Class-D Audio Amplifier with Passive Output Common-Mode Compensation Technique for Wide Output Power Range
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631408openalex-snapshot
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631412openalex-snapshot
An Ultra-Low Voltage Auger-Recombination Enhanced Hot Hole Injection Scheme in Implementing a 3 Bits per Cell e-DRAM CIM Macro for Inference Accelerator
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631425openalex-snapshot
71 GHz-f max β-Ga 2 O 3 -on-SiC RF Power MOSFETs with Record P out =3.1 W/mm and PAE=50.8% at 2 GHz, P out = 2.3 W/mm at 4 GHz, and Low Microwave Noise Figure
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631428openalex-snapshot
Up to 57% Reduction in Effective Resistivity of Word Lines of 3D-NAND Memory by Grain-Size Control, Material Selection, and Seam Removal
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631432openalex-snapshot
Polar Axis Orientation Control of Hafnium-Based Ferroelectric Capacitors with in-Situ AC Electric Bias During Rapid Thermal Annealing
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631433openalex-snapshot
Innovative Barrier Metal-Less Metal Gate Scheme Leading to Highly Reliable Cell Characteristics for 8th Generation 512Gb 3D NAND Flash Memory
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631438openalex-snapshot
Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631441openalex-snapshot
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631444openalex-snapshot
BEOL Compatible Ultra-Low Operating Voltage (0.5 V) and Preconfigured Switching Polarization States in Effective 3 nm Ferroelectric HZO Capacitors
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631454openalex-snapshot
Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631457openalex-snapshot
Field Plate and Package Optimization for GaN Devices and Systems
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631465openalex-snapshot
Assessment of the Transient Self-Heating Effect and its Impact on the Performance of Watt-Level RF Power Amplifier in a FinFET Technology
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631469openalex-snapshot
First Demonstration of Superconducting Nb Contact on Heavily-Doped Group IV Semiconductor
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631470openalex-snapshot
Replacement Metal Gate Process Extendible Beyond 2-nm Node with Superior Gate Conductivity
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631472openalex-snapshot
A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration for Memory and Computing Applications
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631478openalex-snapshot
Integration of Si-Interposer and High Density MIM Capacitor on 2.5D Foveros Face-to-Face Architecture
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631483openalex-snapshot
First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631504openalex-snapshot
Single Metal BCAT Breakthrough to Open a New Era of 12 nm DRAM and Beyond
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631506openalex-snapshot
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size ($\mathbf{25}\times \mathbf{33}\mathbf{mm}^{\mathbf{2}}$) Single-Crystalline Si on SiO 2 by Elevated-Epi
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631509openalex-snapshot
Photon-Mediated Charge Transport and Stability of Physically-Defined and Self-Organized Germanium Quantum Dots/SON Barriers in Few-Hole Regime at $\mathrm{T} > 10\ \mathrm{K}$
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631510openalex-snapshot
A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm2 at 0.60V for Auto-G1 Applications
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631518openalex-snapshot
Mechanical Stress Effects on Dielectric Leakage and Interconnection Integrity in 3D NAND Flash Memory
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631522openalex-snapshot
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631544openalex-snapshot
A Novel Method for Extracting Asymmetric Source and Drain Resistance in IGZO Vertical Channel Transistors
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631550openalex-snapshot
A-IGZO FETs with High Current and Remarkable Stability for Vertical Channel Transistor(VCT) / 3D DRAM Applications
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631551openalex-snapshot
First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (<10ns), Record-Low Energy (<10fJ) of Data Transfer and Ultra-Long Data Retention (>5000s)
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631552openalex-snapshot
A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631556openalex-snapshot
Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577414openalex-snapshot
A 12 V-to-1V Scalable 2N-Phase Buck Converter Using 0V-Stress Balancer with Shortest $I_{\mathrm{L}}$ Balancing Path for Parallel IC Expansion in xPU Systems
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577424openalex-snapshot
Scaling $V_{DD}$ for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577518openalex-snapshot
4nm FinFET CMOS Logic Embedded 1T Contact RRAM
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577586openalex-snapshot
Highly Stackable 3D DRAM of Dual-Gate IGZO 2T0C with Record 3 Bits/Cell and 400s Data Retention
inferred← citeshttps://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577593openalex-snapshot
Record-Thin $(\sim 2 ~\text{nm})$ Wakeup-Free Hzo Ferroelectric Mfm Via Atomic Layer Etching (Ale): Grain Size Enlargement and Ferroelectric Phase Engineering
inferred← citeshttps://doi.org/10.1109/vlsitsa60681.2024.10546439openalex-snapshot
CMOS Scaling by Nanosheet Device Architectures and Backside Engineering
inferred← citeshttps://doi.org/10.1109/vlsitsa69131.2026.11527708openalex-snapshot
On Variability of ML/BL MoS 2 FETs Induced by Channel-Layer-Thickness Fluctuation
inferred← citeshttps://doi.org/10.1109/vlsitsa69131.2026.11527790openalex-snapshot
Titanium as Oxygen Scavenging/Etching Stop Layers to Boost I on of Self-Aligned IGZO Top-Gate Transistors
inferred← citeshttps://doi.org/10.1109/vlsitsa69131.2026.11527906openalex-snapshot
A Novel Gate-injected Ferroelectric Tunnel FET with Ambipolarity Enabling 3D In-Storage Computing and Searching for LLMs
inferred← citeshttps://doi.org/10.1109/vlsitsa69131.2026.11528074openalex-snapshot
Performance Enhancement of Nanosheet/Nanowire RF Transistor Arrays by Backside Metal Layout
inferred← citeshttps://doi.org/10.23919/iwjt66253.2025.11072889openalex-snapshot
Gas/Vapor Phase Epi (VPE), Liquid Phase Epi (LPE) & Solid Phase Epi (SPE) Doping Methods in Si, SiGe and Ge: A Historical Review
inferred← citeshttps://doi.org/10.23919/snw57900.2023.10183944openalex-snapshot
Data Matching Engine for Efficient Big Data Searching Systems Using a RRAM Based Novel Computing Paradigm
inferred← citeshttps://doi.org/10.23919/snw57900.2023.10183964openalex-snapshot
New Understanding of Memory Window Reduction Induced by Ferroelectric Dynamics for HfO2-based 1T1C FeRAM
inferred← citeshttps://doi.org/10.23919/snw65111.2025.11097207openalex-snapshot
High-Performance BEOL-Compatible ALD-IGZO Top-Gate Radio-Frequency Transistors
inferred← citeshttps://doi.org/10.23919/snw65111.2025.11097213openalex-snapshot
Optimizing CFET Parasitic Capacitance and Performance Through Middle Dielectric Isolation and Middle via Integration
inferred← citeshttps://doi.org/10.23919/snw65111.2025.11097229openalex-snapshot
Poly-Si Nanosheet FETs with Vertical C-Shaped Channel Using Pulse Laser Crystallization
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185240openalex-snapshot
First Observation of Ultra-high Polarization (~ 108 μC/cm²) in Nanometer Scaled High Performance Ferroelectric HZO Capacitors with Mo Electrodes
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185250openalex-snapshot
Lg = 60 nm In0.53 Ga0.47 As MBCFETs: From gm_max = 13.7 mS/üm and Q = 180 to virtual-source modeling
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185268openalex-snapshot
A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185269openalex-snapshot
A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and −248.6-dB FoMjitter
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185312openalex-snapshot
First Demonstration of BEOL-Compatible Atomic-Layer-Deposited InGaZnO TFTs with 1.5 nm Channel Thickness and 60 nm Channel Length Achieving ON/OFF Ratio Exceeding 10 11 , SS of 68 mV/dec, Normal-off Operation and High Positive Gate Bias Stability
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185320openalex-snapshot
Record High Active Boron Doping using Low Temperature In-situ CVD: Enabling Sub-5×10−10 Ω-cm2 ρc from Cryogenic (5 K) to Room Temperature
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185321openalex-snapshot
A Wireless, Mechanically Flexible, 25μm-Thick, 65,536-Channel Subdural Surface Recording and Stimulating Microelectrode Array with Integrated Antennas
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185324openalex-snapshot
Novel Bridge Transmission Line Method for Thin-Film Semiconductors: Modelling, Simulation Verification, and Experimental Demonstration
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185341openalex-snapshot
16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir57934.2023.10185352openalex-snapshot
A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074785openalex-snapshot
A 0.184mm 2 $W$-Band Single-RTWO-Based Subharmonic RX Achieving 3.72 dB-NF and I/Q Mismatch < 0.8° in 22 nm CMOS
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074801openalex-snapshot
A Novel Backside Signal Inter/Intra-Cell Routing Method Beyond Backside Power for Angstrom Nodes
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074812openalex-snapshot
A Ka-Band 8-Stream Phased-Array Receiver with Time-Hopping Blocker Rejection for 6G Applications
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074815openalex-snapshot
Wide Memory Window and Steep ISPP Slope (13.2 V and 2.7) of an Aggressively Scaled 3D Ferroelectric NAND (Fenand) Cell for lt;30\text{nm}$ Tier Pitch Scaling
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074825openalex-snapshot
A 0.8\mu\mathrm{m}$ 32Mpixel Always-On CMOS Image Sensor with Windmill-Pattern Edge Extraction and On-Chip DNN
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074832openalex-snapshot
A Monolithic Dual-Layer Pixel Design with BEOL IGZO Transistors Featuring High Dual Conversion Gain Ratio and Scaled Pixel Size for Future Image Sensors
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074838openalex-snapshot
Selective Deposition and Ruthenium Superfill Exploration Beyond A10 Node Interconnects
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074845openalex-snapshot
Towards Understanding Cryogenic Reliability in FinFETs Under Hot Carrier Stress: New Findings on Ge Migration, and Impacts of Tail States Evolution
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074846openalex-snapshot
A Triple-Band Transceiver for Formation Flying Satellite Communication with Dual Circular Polarized Wireless Power and LO Transfer
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074856openalex-snapshot
Critical Role of Quantum Confinement on Transfer Length in Achieving High-Performance In2O3 Transistors with Ultra-Scaled Contacted Gate Pitch
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074858openalex-snapshot
A 33aFrms34pF Base Capacitance, 192fF Input Range 500kHz Sampling Frequencycapacitancetovoltage Converter using a Resonant LC Bridge
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074866openalex-snapshot
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074871openalex-snapshot
A Wireless Power and Synchronized Full-Duplex Data Transceiver IC with 400 Kbps Bidirectional Data Rate Using a Single Inductive Link for Low-Power Systems
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074882openalex-snapshot
A 77 fJ/Bit 8 Gbps Low-Latency Self-Timed Die-to-Die Link for 2.5D and 3D Interconnect in 3nm
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074883openalex-snapshot
Homo-Channel WSe2 n/pFETs with High Performance and On/Off Ratio Using Tunable Doping
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074889openalex-snapshot
First Demonstration of Top T-Gate Beol-Compatible Indium-Oxide RF Transistors with Record Maximum Oscillation Frequency of 70 GHz
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074897openalex-snapshot
A 3nm 125 Tops/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8 and FP16 Digital-CIM Compiler with Multi-Weight Update/Cycle
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074914openalex-snapshot
First Demonstration of Monolithic 3-Tier Nanosheet Transistor Stacking with Split Gate Featuring Tri-State Inverter/Half Sram Functionalities
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074922openalex-snapshot
Orthogonal $\mathbf{V}_{\mathbf{T}}$ Tuning for Oxide Semiconductor 2T Gain Cell Enabled by Interface Dipole Engineering
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074928openalex-snapshot
A 10W 3.8-5V Input IVR Chiplet with 93%-Peak-Efficiency and 3.2A/mm2 Density Featuring Wide Load Range and Adaptive Ganging for 2.5D/3D Vertical Power Delivery
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074933openalex-snapshot
A 16NM 550-1320 BTOPS/W NPU Exploiting Training-Free Structured Bit-Level Sparsity and Dynamic Dataflow Processing
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074962openalex-snapshot
A Hybrid Monolithic 3D Integration of 2T0C DRAM and RRAM Chip for High-Precision In-Memory Point Cloud Acceleration with Ultra-Fine-Grained Dataflow
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074963openalex-snapshot
A 425pW, 0.3V, 32kHz Crystal Oscillator in 22nm FDSOI with Adaptive Pulse Injection and Amplitude Regulation Across −40°C to 125°C
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074978openalex-snapshot
DERMIS: A Flexible Fully-Integrated $\mathbf{6 0 0} \bm{\mu} \mathbf{m}$-Resolution Per-Taxel Slip-to-Spikes Tactile Sensor Readout on A-IGZO TFT for Large-Area High-Density Electronic Skins
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074985openalex-snapshot
A 22nm 41.8TFLOPS/W AI-Edge Transformer/CNN Nonvolatile-Processor Using QKV-Softmax-Layer-Fused Hybrid ReRAM-CIM and Concurrent-Transpose/Non-Transpose SRAM-CIM
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075009openalex-snapshot
Process Insights into 3D-DRAM with Vertical Bit Line and Scalable GAA Transistor
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075020openalex-snapshot
A 2-Transistor-1-Modulator (2T1m) Electronic-Photonic Hybrid Memory Architecture for Deep Neural Network Cim and Very Large-Scale Transformers
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075032openalex-snapshot
Highly Scalable and Reliable Cell Characteristics for 1Tb 9Th Generation 3D-NAND Flash Memory
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075034openalex-snapshot
High-Performance Monolithic 3D Integrated Red μLEDoS Display for AR/VR
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075052openalex-snapshot
Compressive Diffusion Break Stressor for Gate-All-Around Nanosheet pFET Transistor Performance Improvement
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075056openalex-snapshot
First Direct Observation of Two Different Hydrogen-Related Processes Corresponding to the Negative V TH Shift Under PBTI Stress in IGZO Transistors by Pd Hydrogen Spillover
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075080openalex-snapshot
First Demonstration of 2-floor GAA In2O3 Nanosheet FET Enabled by TiN Sacrificial Layers and Fluorine Passivation
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075099openalex-snapshot
FeRAM Capacitor with Novel Low-Power, Non-destructive and High Endurance Read operation for High-density Embedded Memory
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075113openalex-snapshot
A 22nm 25.08TOPS/W Multi-Task Transformer Accelerator with Mixed Precision Structured Sparsity and Two-Stage Task-Adaptive Power Management
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075121openalex-snapshot
38kbps Multi-Access Magnetoelectric Backscatter Communication with Non-Interrupted WPT for a Network of Miniature Wireless Bio-Implants
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075140openalex-snapshot
A Temperature-Insensitive Period-Modulation CDC with DLL-Based Comparator Delay Compensation Achieving 53.5ppm/°C without Calibration
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075146openalex-snapshot
Assessment on Nanosheet Transistor Variants Beyond 2nm Node
inferred← citeshttps://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075161openalex-snapshot
Unified Physics-Based CFET Thermal SPICE Considering BEOL, Substrate, and BSPDN Using Adiabatic Cones
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