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FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/dsn.2011.5958219openalex-snapshot
Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system
inferredcites →https://doi.org/10.1109/hpca.2010.5416645openalex-snapshot
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
inferredcites →https://doi.org/10.1109/hpca.2011.5749742openalex-snapshot
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system
inferredcites →https://doi.org/10.1109/hpca.2012.6168941openalex-snapshot
Efficient scrub mechanisms for error-prone emerging memories
inferredcites →https://doi.org/10.1109/hpca.2012.6169027openalex-snapshot
Improving write operations in MLC phase change memory
inferredcites →https://doi.org/10.1109/iccd.2011.6081394openalex-snapshot
Energy-efficient multi-level cell phase-change memory system with data encoding
inferredcites →https://doi.org/10.1109/iedm.2007.4418933openalex-snapshot
Statistical analysis and modeling of programming and retention in PCM arrays
inferredcites →https://doi.org/10.1109/iedm.2007.4418973openalex-snapshot
Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory
inferredcites →https://doi.org/10.1109/imw.2010.5488329openalex-snapshot
Impact of material composition on the write performance of phase-change memory devices
inferredcites →https://doi.org/10.1109/isca.2012.6237003openalex-snapshot
BOOM: Enabling mobile memory based low-power server DIMMs
inferredcites →https://doi.org/10.1109/isca.2012.6237004openalex-snapshot
Towards energy-proportional datacenter memory with mobile DRAM
inferredcites →https://doi.org/10.1109/isscc.2012.6176872openalex-snapshot
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth
inferredcites →https://doi.org/10.1109/jssc.1976.1050739openalex-snapshot
On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
inferredcites →https://doi.org/10.1109/jssc.2005.859016openalex-snapshot
Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory
inferredcites →https://doi.org/10.1109/jssc.2008.2006439openalex-snapshot
A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage
inferredcites →https://doi.org/10.1109/mcas.2009.935695openalex-snapshot
Charge Pump Circuits: An Overview on Design Strategies and Topologies
inferredcites →https://doi.org/10.1109/pact.2011.71openalex-snapshot
Memory Architecture for Integrating Emerging Memory Technologies
inferredcites →https://doi.org/10.1109/vlsit.2010.5556227openalex-snapshot
MLC PRAM with SLC write-speed and robust read scheme
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1815961.1815980openalex-snapshot
Use ECP, not ECC, for hard failures in resistive memories
inferredcites →https://doi.org/10.1145/2155620.2155642openalex-snapshot
Preventing PCM banks from seizing too much power
inferredcites →https://doi.org/10.1145/2366231.2337164openalex-snapshot
Towards energy-proportional datacenter memory with mobile DRAM
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-42234-9_10openalex-snapshot
Write Mode Aware Loop Tiling for High-Performance Low-Power Volatile PCM in Embedded Systems
inferred← citeshttps://doi.org/10.1007/978-3-032-13615-2_58openalex-snapshot
Comparison of LLMs on Financial Professional Tests
inferred← citeshttps://doi.org/10.1007/978-3-319-46922-5_28openalex-snapshot
XB+-Tree: A Novel Index for PCM/DRAM-Based Hybrid Memory
inferred← citeshttps://doi.org/10.1007/s11390-015-1508-3openalex-snapshot
Improving the Performance and Energy Efficiency of Phase Change Memory Systems
inferred← citeshttps://doi.org/10.1007/s11390-015-1509-2openalex-snapshot
A Survey of Phase Change Memory Systems
inferred← citeshttps://doi.org/10.1007/s11704-014-4185-4openalex-snapshot
Exploiting write power asymmetry to improve phase change memory system performance
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.05.006openalex-snapshot
Write reconstruction for write throughput improvement on MLC PCM based main memory
inferred← citeshttps://doi.org/10.1088/2631-8695/ad0fc4openalex-snapshot
OML-PCM: optical multi-level phase change memory architecture for embedded computing systems
inferred← citeshttps://doi.org/10.1109/access.2023.3317884openalex-snapshot
Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD
inferred← citeshttps://doi.org/10.1109/aspdac.2016.7427985openalex-snapshot
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read
inferred← citeshttps://doi.org/10.1109/ca.2015.22openalex-snapshot
Efficient Tree Indexing for PCM-Based Memory Systems
inferred← citeshttps://doi.org/10.1109/dsn.2014.32openalex-snapshot
Mitigating Write Disturbance in Super-Dense Phase Change Memories
inferred← citeshttps://doi.org/10.1109/dsn.2016.27openalex-snapshot
ReadDuo: Constructing Reliable MLC Phase Change Memory through Fast and Robust Readout
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056042openalex-snapshot
Reducing read latency of phase change memory via early read and Turbo Read
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446056openalex-snapshot
CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM
inferred← citeshttps://doi.org/10.1109/hpca.2017.45openalex-snapshot
Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor
inferred← citeshttps://doi.org/10.1109/iccd.2018.00019openalex-snapshot
Cap: Exploiting Data Correlations to Improve the Performance and Endurance of SSD RAID
inferred← citeshttps://doi.org/10.1109/icpp.2016.25openalex-snapshot
Tetris Write: Exploring More Write Parallelism Considering PCM Asymmetries
inferred← citeshttps://doi.org/10.1109/isca.2014.6853194openalex-snapshot
A low power and reliable charge pump design for Phase Change Memories
inferred← citeshttps://doi.org/10.1109/isca.2014.6853228openalex-snapshot
Reducing access latency of MLC PCMs through line striping
inferred← citeshttps://doi.org/10.1109/isca.2016.66openalex-snapshot
Boosting Access Parallelism to PCM-Based Main Memory
inferred← citeshttps://doi.org/10.1109/micro.2018.00063openalex-snapshot
Exploring and Optimizing Chipkill-Correct for Persistent Memory Based on High-Density NVRAMs
inferred← citeshttps://doi.org/10.1109/nanoarch.2014.6880482openalex-snapshot
Compression architecture for bit-write reduction in non-volatile memory technologies
inferred← citeshttps://doi.org/10.1109/nas.2016.7549417openalex-snapshot
Reducing Read Latency in MLC PCM
inferred← citeshttps://doi.org/10.1109/nvmsa.2015.7304373openalex-snapshot
Improving MLC PCM write throughput by write reconstruction
inferred← citeshttps://doi.org/10.1109/tc.2015.2479605openalex-snapshot
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems
inferred← citeshttps://doi.org/10.1109/tc.2017.2677903openalex-snapshot
Time and Space-Efficient Write Parallelism in PCM by Exploiting Data Patterns
inferred← citeshttps://doi.org/10.1109/tc.2019.2900036openalex-snapshot
Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM
inferred← citeshttps://doi.org/10.1109/tcad.2017.2762921openalex-snapshot
DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance
inferred← citeshttps://doi.org/10.1109/tcad.2018.2883981openalex-snapshot
A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory
inferred← citeshttps://doi.org/10.1109/tcad.2019.2953948openalex-snapshot
Multitoken-Based Power Management for NAND Flash Storage Devices
inferred← citeshttps://doi.org/10.1109/tmscs.2015.2498549openalex-snapshot
Hybrid Main Memory for High Bandwidth Multi-Core System
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2467157openalex-snapshot
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM
inferred← citeshttps://doi.org/10.1109/vlsid.2017.6openalex-snapshot
DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency
inferred← citeshttps://doi.org/10.1145/2465554.2465564openalex-snapshot
Compiler directed write-mode selection for high performance low power volatile PCM
inferred← citeshttps://doi.org/10.1145/2485922.2485959openalex-snapshot
Bit mapping for balanced PCM cell programming
inferred← citeshttps://doi.org/10.1145/2491899.2465564openalex-snapshot
Compiler directed write-mode selection for high performance low power volatile PCM
inferred← citeshttps://doi.org/10.1145/2499369.2465564openalex-snapshot
Compiler directed write-mode selection for high performance low power volatile PCM
inferred← citeshttps://doi.org/10.1145/2508148.2485959openalex-snapshot
Bit mapping for balanced PCM cell programming
inferred← citeshttps://doi.org/10.1145/2540708.2540726openalex-snapshot
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
inferred← citeshttps://doi.org/10.1145/2627369.2627630openalex-snapshot
Making B + -tree efficient in PCM-based main memory
inferred← citeshttps://doi.org/10.1145/2678373.2665713openalex-snapshot
Reducing access latency of MLC PCMs through line striping
inferred← citeshttps://doi.org/10.1145/2678373.2665731openalex-snapshot
A low power and reliable charge pump design for phase change memories
inferred← citeshttps://doi.org/10.1145/2820610openalex-snapshot
Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM
inferred← citeshttps://doi.org/10.1145/2997648openalex-snapshot
Power-Utility-Driven Write Management for MLC PCM
inferred← citeshttps://doi.org/10.1145/3007787.3001211openalex-snapshot
Boosting access parallelism to PCM-based main memory
inferred← citeshttps://doi.org/10.1145/3060403.3060412openalex-snapshot
Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change Memories
inferred← citeshttps://doi.org/10.1145/3200139openalex-snapshot
Write Energy Reduction for PCM via Pumping Efficiency Improvement
inferred← citeshttps://doi.org/10.1145/3240302.3240310openalex-snapshot
Design guidelines for high-performance SCM hierarchies
inferred← citeshttps://doi.org/10.1145/3358180openalex-snapshot
Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change Memories
inferred← citeshttps://doi.org/10.1145/3381898.3397210openalex-snapshot
Improving phase change memory performance with data content aware access
inferred← citeshttps://doi.org/10.1145/3381898.3397215openalex-snapshot
Exploiting inter- and intra-memory asymmetries for data mapping in hybrid tiered-memories
inferred← citeshttps://doi.org/10.1145/3466752.3480054openalex-snapshot
LADDER: Architecting Content and Location-aware Writes for Crossbar Resistive Memories
inferred← citeshttps://doi.org/10.1145/3533252openalex-snapshot
Architecting Optically Controlled Phase Change Memory
inferred← citeshttps://doi.org/10.1155/2022/9552517openalex-snapshot
PCM-2R: Accelerating MLC PCM Writes via Data Reshaping and Remapping
inferred← citeshttps://doi.org/10.1504/ijcaet.2016.079392openalex-snapshot
A survey of power management techniques for phase change memory
inferred← citeshttps://doi.org/10.32604/csse.2021.017224openalex-snapshot
NVM Storage in IoT Devices: Opportunities and Challenges
inferred← citeshttps://doi.org/10.48550/arxiv.1309.3785openalex-snapshot
Energy Saving Techniques for Phase Change Memory (PCM)
inferred← citeshttps://doi.org/10.48550/arxiv.1909.12221openalex-snapshot
Storage Class Memory: Principles, Problems, and Possibilities
inferred← citeshttps://doi.org/10.48550/arxiv.2111.02325openalex-snapshot
Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study
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