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Conservative Open-Page Policy for Mixed Time-Criticality Memory Controllers
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inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_22openalex-snapshot
Reducing NoC and Memory Contention for Manycores
inferred← citeshttps://doi.org/10.1007/978-94-017-7267-9_17openalex-snapshot
NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications
inferred← citeshttps://doi.org/10.1007/978-94-017-7358-4_17-1openalex-snapshot
NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications
inferred← citeshttps://doi.org/10.1007/s10617-018-9206-3openalex-snapshot
DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems
inferred← citeshttps://doi.org/10.1007/s11241-015-9227-yopenalex-snapshot
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources
inferred← citeshttps://doi.org/10.1007/s11241-015-9235-yopenalex-snapshot
Architecture and analysis of a dynamically-scheduled real-time memory controller
inferred← citeshttps://doi.org/10.1007/s11241-016-9253-4openalex-snapshot
A composable worst case latency analysis for multi-rank DRAM devices under open row policy
inferred← citeshttps://doi.org/10.1007/s11241-017-9277-4openalex-snapshot
Isolation scheduling on multicores: model and scheduling approaches
inferred← citeshttps://doi.org/10.1007/s11241-019-09338-8openalex-snapshot
Reduced latency DRAM for multi-core safety-critical real-time systems
inferred← citeshttps://doi.org/10.1016/j.jss.2015.11.019openalex-snapshot
Scalable and efficient configuration of time-division multiplexed resources
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.04.001openalex-snapshot
Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC
inferred← citeshttps://doi.org/10.1109/ecrts.2014.18openalex-snapshot
Dynamic Command Scheduling for Real-Time Memory Controllers
inferred← citeshttps://doi.org/10.1109/ecrts.2014.37openalex-snapshot
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00030openalex-snapshot
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA
inferred← citeshttps://doi.org/10.1109/indin.2016.7819142openalex-snapshot
Mixed-criticality transactional memory controller for embedded systems
inferred← citeshttps://doi.org/10.1109/isorc.2016.38openalex-snapshot
Mixed-Criticality Systems as a Service for Non-critical Tasks
inferred← citeshttps://doi.org/10.1109/rtas.2014.6925999openalex-snapshot
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms
inferred← citeshttps://doi.org/10.1109/rtas.2015.7108439openalex-snapshot
An efficient configuration methodology for time-division multiplexed single resources
inferred← citeshttps://doi.org/10.1109/rtas.2015.7108453openalex-snapshot
Reverse-engineering embedded memory controllers through latency-based analysis
inferred← citeshttps://doi.org/10.1109/rtas.2015.7108454openalex-snapshot
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems
inferred← citeshttps://doi.org/10.1109/rtas.2016.7461339openalex-snapshot
Memory Servers for Multicore Systems
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00011openalex-snapshot
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors
inferred← citeshttps://doi.org/10.1109/rtss.2013.44openalex-snapshot
Worst Case Analysis of DRAM Latency in Multi-requestor Systems
inferred← citeshttps://doi.org/10.1109/rtss.2014.23openalex-snapshot
A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study
inferred← citeshttps://doi.org/10.1109/rtss.2015.21openalex-snapshot
An Isolation Scheduling Model for Multicores
inferred← citeshttps://doi.org/10.1109/rtss.2018.00062openalex-snapshot
On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?
inferred← citeshttps://doi.org/10.1109/sies.2013.6601469openalex-snapshot
Identifying the sources of unpredictability in COTS-based multicore systems
inferred← citeshttps://doi.org/10.1109/sies.2014.6871199openalex-snapshot
Dynamic budgeting for settling DRAM contention of co-running hard and soft real-time tasks
inferred← citeshttps://doi.org/10.1109/sies.2016.7509441openalex-snapshot
Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems
inferred← citeshttps://doi.org/10.1145/3466752.3480069openalex-snapshot
A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96600openalex-snapshot
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
inferred← citeshttps://doi.org/10.70675/5a9cee0bz162ez41ebz9f00z288fb5fd7460openalex-snapshot
CoqDRAM - A Foundation for Designing Formally Proven Memory Controllers
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