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A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4419-8207-0openalex-snapshot
Memory Controllers for Real-Time Embedded Systems
inferredcites →https://doi.org/10.1007/s11241-011-9129-6openalex-snapshot
Making DRAM refresh predictable
inferredcites →https://doi.org/10.1063/1.1774721openalex-snapshot
The Cryogenic System of the Herschel Extended Payload Module
inferredcites →https://doi.org/10.1109/codes-isss.2013.6658989openalex-snapshot
A reconfigurable real-time SDRAM controller for mixed time-criticality systems
inferredcites →https://doi.org/10.1109/ecrts.2014.37openalex-snapshot
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/les.2010.2041634openalex-snapshot
An Analyzable Memory Controller for Hard Real-Time CMPs
inferredcites →https://doi.org/10.1109/mm.2009.74openalex-snapshot
A Benchmark Characterization of the EEMBC Benchmark Suite
inferredcites →https://doi.org/10.1109/rtas.2014.6925998openalex-snapshot
Bounding memory interference delay in COTS-based multi-core systems
inferredcites →https://doi.org/10.1109/rtas.2014.6925999openalex-snapshot
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms
inferredcites →https://doi.org/10.1109/rtss.2007.35openalex-snapshot
Techniques for Multiprocessor Global Schedulability Analysis
inferredcites →https://doi.org/10.1109/rtss.2007.47openalex-snapshot
Preemptive Scheduling of Multi-criticality Systems with Varying Degrees of Execution Time Assurance
inferredcites →https://doi.org/10.1109/rtss.2013.44openalex-snapshot
Worst Case Analysis of DRAM Latency in Multi-requestor Systems
inferredcites →https://doi.org/10.1109/sies.2013.6601468openalex-snapshot
Deconstructing bus access control policies for Real-Time multicores
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1555754.1555764openalex-snapshot
Hardware support for WCET analysis of hard real-time multicore systems
inferredcites →https://doi.org/10.1145/2370816.2370869openalex-snapshot
A software memory partition approach for eliminating bank-level interference in multicore systems
inferredcites →https://doi.org/10.1145/2435227.2435260openalex-snapshot
Timing effects of DDR memory systems in hard real-time multicore architectures
inferredcites →https://doi.org/10.2514/6.2009-1882openalex-snapshot
NASA Study on Flight Software Complexity
inferredcites →https://doi.org/10.5555/2485288.2485418openalex-snapshot
Conservative open-page policy for mixed time-criticality memory controllers
inferredcites →https://doi.org/10.7873/date.2013.118openalex-snapshot
Conservative Open-Page Policy for Mixed Time-Criticality Memory Controllers
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-32094-6_9openalex-snapshot
Conclusions and Future Work
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A composable worst case latency analysis for multi-rank DRAM devices under open row policy
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Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning
inferred← citeshttps://doi.org/10.1007/s11241-017-9280-9openalex-snapshot
Addressing isolation challenges of non-blocking caches for multicore real-time systems
inferred← citeshttps://doi.org/10.1007/s11241-019-09338-8openalex-snapshot
Reduced latency DRAM for multi-core safety-critical real-time systems
inferred← citeshttps://doi.org/10.1007/s11241-020-09351-2openalex-snapshot
Supporting I/O and IPC via fine-grained OS isolation for mixed-criticality real-time tasks
inferred← citeshttps://doi.org/10.1007/s11241-023-09411-3openalex-snapshot
A formal framework to design and prove trustworthy memory controllers
inferred← citeshttps://doi.org/10.1007/s11241-024-09425-5openalex-snapshot
Mcti: mixed-criticality task-based isolation
inferred← citeshttps://doi.org/10.1049/iet-cdt.2018.5031openalex-snapshot
High performance and predictable memory controller for multicore mixed‐criticality real‐time systems
inferred← citeshttps://doi.org/10.1109/cpsna.2015.24openalex-snapshot
MEDUSA: A Predictable and High-Performance DRAM Controller for Multicore Based Embedded Systems
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00047openalex-snapshot
Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case Study
inferred← citeshttps://doi.org/10.1109/ecrts.2016.8openalex-snapshot
Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643473openalex-snapshot
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/indin.2016.7819142openalex-snapshot
Mixed-criticality transactional memory controller for embedded systems
inferred← citeshttps://doi.org/10.1109/rtas.2016.7461323openalex-snapshot
Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning
inferred← citeshttps://doi.org/10.1109/rtas.2016.7461341openalex-snapshot
Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers
inferred← citeshttps://doi.org/10.1109/rtas.2016.7461361openalex-snapshot
Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtas.2017.12openalex-snapshot
A Requests Bundling DRAM Controller for Mixed-Criticality Systems
inferred← citeshttps://doi.org/10.1109/rtas.2017.14openalex-snapshot
Allowing Shared Libraries While Supporting Hardware Isolation in Multicore Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00-15openalex-snapshot
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
inferred← citeshttps://doi.org/10.1109/rtas52030.2021.00030openalex-snapshot
Simultaneous Multithreading in Mixed-Criticality Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtcsa52859.2021.00021openalex-snapshot
A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems
inferred← citeshttps://doi.org/10.1109/rtss.2015.13openalex-snapshot
Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling
inferred← citeshttps://doi.org/10.1109/rtss.2016.015openalex-snapshot
Reconciling the Tension Between Hardware Isolation and Data Sharing in Mixed-Criticality, Multicore Systems
inferred← citeshttps://doi.org/10.1109/rtss.2018.00062openalex-snapshot
On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?
inferred← citeshttps://doi.org/10.1109/rtss46320.2019.00045openalex-snapshot
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems
inferred← citeshttps://doi.org/10.1109/rtss59052.2023.00031openalex-snapshot
Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems
inferred← citeshttps://doi.org/10.1109/sies.2016.7509441openalex-snapshot
Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems
inferred← citeshttps://doi.org/10.1109/tc.2016.2616307openalex-snapshot
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration
inferred← citeshttps://doi.org/10.1109/tcad.2018.2857379openalex-snapshot
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems
inferred← citeshttps://doi.org/10.1145/3035481openalex-snapshot
A Single-Tier Virtual Queuing Memory Controller Architecture for Heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.1145/3131347openalex-snapshot
A Survey of Research into Mixed Criticality Systems
inferred← citeshttps://doi.org/10.1145/3139258.3139268openalex-snapshot
Supporting mode changes while providing hardware isolation in mixed-criticality multicore systems
inferred← citeshttps://doi.org/10.1145/3158208openalex-snapshot
A Comparative Study of Predictable DRAM Controllers
inferred← citeshttps://doi.org/10.1145/3269982openalex-snapshot
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems
inferred← citeshttps://doi.org/10.1145/3273905.3273911openalex-snapshot
Supporting I/O and IPC via Fine-Grained OS Isolation for Mixed-Criticality Real-Time Tasks
inferred← citeshttps://doi.org/10.1145/3319804openalex-snapshot
A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets
inferred← citeshttps://doi.org/10.1145/3398665openalex-snapshot
Multi-core Devices for Safety-critical Systems
inferred← citeshttps://doi.org/10.1145/3488423.3519322openalex-snapshot
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance
inferred← citeshttps://doi.org/10.1145/3534879.3534907openalex-snapshot
A Coq Framework for More Trustworthy DRAM Controllers
inferred← citeshttps://doi.org/10.23919/date.2017.7927122openalex-snapshot
Design and implementation of a fair credit-based bandwidth sharing scheme for buses
inferred← citeshttps://doi.org/10.5821/dissertation-2117-125025openalex-snapshot
Enhancing timing analysis for COTS multicores for safety-related industry : a software approach
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96600openalex-snapshot
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
inferred← citeshttps://doi.org/10.6100/ir850540openalex-snapshot
Design and formal analysis of real-time memory controllers
inferred← citeshttps://doi.org/10.70675/5a9cee0bz162ez41ebz9f00z288fb5fd7460openalex-snapshot
CoqDRAM - A Foundation for Designing Formally Proven Memory Controllers
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