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Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Compilation Techniques for Reconfigurable Architectures
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High-Level Synthesis: from Algorithm to Digital Circuit
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Loop Tiling for Parallelism
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Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations
inferredcites →https://doi.org/10.1007/978-3-642-00722-4_17openalex-snapshot
Precise Management of Scratchpad Memories for Localising Array Accesses in Scientific Codes
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Dataflow analysis of array and scalar references
inferredcites →https://doi.org/10.1016/s0167-8191(97)00089-6openalex-snapshot
Memory size reduction through storage order optimization for embedded parallel multimedia applications
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Parametric integer programming
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Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool
inferredcites →https://doi.org/10.1109/icvd.2003.1183177openalex-snapshot
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations
inferredcites →https://doi.org/10.1109/pact.2005.13openalex-snapshot
Communication optimizations for fine-grained UPC applications
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Effective communication coalescing for data-parallel applications
inferredcites →https://doi.org/10.1145/1345206.1345210openalex-snapshot
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories
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A mapping path for multi-GPGPU accelerated computers from a portable high level programming abstraction
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A reuse-aware prefetching scheme for scratchpad memory
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Compiler-directed scratch pad memory hierarchy design and management
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Scanning polyhedra without Do-loops
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Beyond Do Loops: Data Transfer Generation with Convex Array Regions
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Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes
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Loop Parallelization Techniques for FPGA Accelerator Synthesis
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Study and evaluation of automatic offloading for function blocks of applications
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Automatic offloading method of loop statements of software to FPGA
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Study and evaluation of automatic GPU offloading method from various language applications
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Study and evaluation of FPGA reconfiguration during service operation for environment-adaptive software
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Study and evaluation of quantum computer automatic offloading of specific calculation processing for environmental adaptation
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Hardware design and analysis of efficient loop coarsening and border handling for image processing
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Derivation of efficient FSM from loop nests
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Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays
inferred← citeshttps://doi.org/10.1109/scam.2013.6648190openalex-snapshot
GeCoS: A framework for prototyping custom hardware design flows
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A Structured Approach Towards Big Data Identification
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Memory reuse optimizations in the R-Stream compiler
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Data-reuse Optimizations for pipelined Tiling with Parametric Tile Sizes
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Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning
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Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
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Optimizing Affine Control With Semantic Factorizations
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Evaluation of Reconfiguration Steps on Operation for Environment Adaptive Software
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Enabling FPGAs for the Masses
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Optimizing Memory Performance of Xilinx FPGAs under Vitis
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Exploring the Impact of Affine Loop Transformations in Qubit Allocation
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