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An Area-efficient Network Interface for a TDM-based Network-on-Chip
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inferred← citeshttps://doi.org/10.1007/978-3-030-18656-2_22openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10586-019-02924-2openalex-snapshot
Network adapter architectures in network on chip: comprehensive literature review
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Patmos: a time-predictable microprocessor
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T-CREST: Time-predictable multi-core architecture for embedded systems
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Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip
inferred← citeshttps://doi.org/10.1109/dsd60849.2023.00112openalex-snapshot
Implementation and Verification of the Argo Network-on-Chip in Chisel
inferred← citeshttps://doi.org/10.1109/ecctd.2015.7300101openalex-snapshot
The Argo NOC: Combining TDM and GALS
inferred← citeshttps://doi.org/10.1109/fpl.2016.7577378openalex-snapshot
XNoC: A non-intrusive TDM circuit-switched Network-on-Chip
inferred← citeshttps://doi.org/10.1109/isorc.2014.43openalex-snapshot
A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/isorc.2015.15openalex-snapshot
Message Passing on a Time-predictable Multicore Processor
inferred← citeshttps://doi.org/10.1109/isorc61049.2024.10551364openalex-snapshot
Exploration of Network Interface Architectures for a Real-Time Network-on-Chip
inferred← citeshttps://doi.org/10.1109/isorc70347.2026.11605558openalex-snapshot
SlimFlit: A simple Network-on-Chip for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/isorcw.2015.57openalex-snapshot
Models of Communication for Multicore Processors
inferred← citeshttps://doi.org/10.1109/isvlsi49217.2020.00028openalex-snapshot
Path-Spreading Search Algorithm and ASIP Approach for Connection Allocation in TDM-NoCs
inferred← citeshttps://doi.org/10.1109/isvlsi51109.2021.00073openalex-snapshot
Minimized Region of Path-search Algorithm for ASIP-based Connection Allocator in NoCs
inferred← citeshttps://doi.org/10.1109/ngcas.2017.73openalex-snapshot
Timing Organization of a Real-Time Multicore Processor
inferred← citeshttps://doi.org/10.1109/nocs.2014.7008774openalex-snapshot
A loosely synchronizing asynchronous router for TDM-scheduled NOCs
inferred← citeshttps://doi.org/10.1109/nocs.2016.7579324openalex-snapshot
An area-efficient TDM NoC supporting reconfiguration for mode changes
inferred← citeshttps://doi.org/10.1109/norchip.2014.7004742openalex-snapshot
Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools
inferred← citeshttps://doi.org/10.1109/norchip.2018.8573463openalex-snapshot
Time-Predictable Distributed Shared Memory for Multi-Core Processors
inferred← citeshttps://doi.org/10.1109/norchip.2018.8573470openalex-snapshot
Analysis of Synchronous-Asynchronous NoC for the Dark Silicon Era
inferred← citeshttps://doi.org/10.1109/pdp.2016.36openalex-snapshot
Avionics Applications on a Time-Predictable Chip-Multiprocessor
inferred← citeshttps://doi.org/10.1109/recosoc.2016.7533895openalex-snapshot
Reconfiguration in FPGA-based multi-core platforms for hard real-time applications
inferred← citeshttps://doi.org/10.1109/socc.2013.6749691openalex-snapshot
High-performance adaption of ARM processors into Network-on-Chip architectures
inferred← citeshttps://doi.org/10.1109/socc46988.2019.1570555815openalex-snapshot
Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs
inferred← citeshttps://doi.org/10.1109/socc46988.2019.1570558594openalex-snapshot
A Network on Chip Adapter for Real-Time and Safety-Critical Applications
inferred← citeshttps://doi.org/10.1109/tc.2017.2759203openalex-snapshot
Adas on Cots with OpenCL: A Case Study with Lane Detection
inferred← citeshttps://doi.org/10.1109/tetc.2017.2765825openalex-snapshot
High Performance Dynamic Resource Allocation for Guaranteed Service in Network-on-Chips
inferred← citeshttps://doi.org/10.1109/tnet.2021.3073460openalex-snapshot
A Quantitative Analysis of Interfaces to Time-Triggered Communication Buses
inferred← citeshttps://doi.org/10.1109/tpds.2016.2623619openalex-snapshot
Survey on Real-Time Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2405614openalex-snapshot
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
inferred← citeshttps://doi.org/10.22456/2175-2745.43468openalex-snapshot
XIRU: Interface de Rede Extensível para Integração de Núcleos a uma Rede-em-Chip
inferred← citeshttps://doi.org/10.3390/sym16010127openalex-snapshot
Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip
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