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Is Split Manufacturing Secure?

https://doi.org/10.7873/date.2013.261

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CIST: A Threat Modelling Approach for Hardware Supply Chain Security

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Design Constraint Based Attacks

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Defenses Against Design Constraint Based Attacks

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Satisfiability Based Attacks

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Introduction

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Reconfigurability for Static Camouflaging

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Heterogeneous 2.5D and 3D Integration for Securing Hardware and Data

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Obfuscating the Hierarchy of a Digital IP

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Background

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Logic-Locking Insertion and Assessment

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Making a Case for Logic Locking

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UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks

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Hintergrundinformationen

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Materials for Hardware Security

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Advances in Logic Locking

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Introduction

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ReBO-Driven IC Design: Leveraging Reconfigurable Logic for Obfuscation

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X-CHAIN: Enhancing Electronic Supply Chain Security with 3D X-Ray Inspection and Blockchain Integration

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Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation

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Split Manufacturing

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Obfuscated Built-In Self-authentication

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3D/2.5D IC-Based Obfuscation

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VLSI Test and Hardware Security Background for Hardware Obfuscation

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Physical Unclonable Functions and Intellectual Property Protection Techniques

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Key Update at Train Stations: Two-Layer Dynamic Key Update Scheme for Secure Train Communications

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Hardware Obfuscation Methods for Hardware Trojan Prevention and Detection

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Deterrent Approaches Against Hardware Trojan Insertion

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Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks

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Hardware Security for IC Piracy: Logic Locking Past, Present and Opportunity

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Spear and Shield: Evolution of Integrated Circuit Camouflaging

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Manufacturing and Security Challenges in 3D Printing

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A Survey on Logic-Locking Characteristics and Attacks

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On the Limitations of Obfuscating Redundant Circuits in Frustrating Hardware Trojan Implantation

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Internet of Things World: A New Security Perspective

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Hardware Obfuscation

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A survey of hardware Trojan threat and defense

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VLSI supply chain security risks and mitigation techniques: A survey

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A Review on HT Attacks in PLD and ASIC Designs with Potential Defence Solutions

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A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

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How secure is split manufacturing in preventing hardware trojan?

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DOST: Dynamically obfuscated wrapper for split test against IC piracy

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From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

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Routing perturbation for enhanced security in split manufacturing

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Concerted wire lifting: Enabling secure and cost-effective split manufacturing

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A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion

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A split-foundry asynchronous FPGA

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Analysis of Security of Split Manufacturing using Machine Learning

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Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL

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GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection

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Hybrid Obfuscation of Chiplet-Based Systems

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TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns

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Combating Data Leakage Trojans in Sequential Circuits Through Randomized Encoding

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Can flexible, domain specific programmable logic prevent IP theft?

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Split-Fabric: A Novel Wafer-Scale Hardware Obfuscation Methodology using Silicon Interconnect Fabric

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Design Obfuscation versus Test

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Identifying Sat Resilient Blocks Through LUT Switching Analysis for Breaking Compound Logic Locking Schemes

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Building trusted ICs using split fabrication

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Split-fabrication obfuscation: Metrics and techniques

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Efficient and secure intellectual property (IP) design with split fabrication

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Efficient and secure split manufacturing via obfuscated built-in self-authentication

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Automatic obfuscated cell layout for trusted split-foundry design

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Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits

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Ephemeral Key-based Hybrid Hardware Obfuscation

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Design and Analysis of Hardware Trojan Threats in Reconfigurable Hardware

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Making split fabrication synergistically secure and manufacturable

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Making split fabrication synergistically secure and manufacturable

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Rethinking split manufacturing: An information-theoretic approach with secure layout techniques

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Front-end-of-line attacks in split manufacturing

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Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality

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Split Compilation for Security of Quantum Circuits

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Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking

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Functional Locking through Omission: From HLS to Obfuscated Design

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Reduction of Data Leakage Trojans in Modulation Scheme of TDMA using Encoding and Decoding

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Hardware security and split fabrication

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Security aspects of analog and mixed-signal circuits

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Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection?

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An overview of hardware intellectual property protection

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PUF Modeling Attack using Active Learning

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Invariance Checking Based Trojan Detection Method for Three-Dimensional Integrated Circuits

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Enhancing SAT-Attack Resiliency and Cost-Effectiveness of Reconfigurable-Logic-Based Circuit Obfuscation

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A Novel Logical Locking Technique Against Key-Guessing Attacks

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A Holistic Blockchain Based IC Traceability Technique

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Preventing integrated circuit piracy via custom encoding of hardware instruction set

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SATConda: SAT to SAT-Hard Clause Translator

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A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans

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A Secure Design Methodology to Prevent Targeted Trojan Insertion during Fabrication

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A Novel Tampering Attack on AES Cores with Hardware Trojans

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Hardware IP Protection Using Logic Encryption and Watermarking

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Reconfiguration-Based VLSI Design for Security

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Regaining Trust in VLSI Design: Design-for-Trust Techniques

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Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain

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Hardware Trojan Attacks: Threat Analysis and Countermeasures

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A Primer on Hardware Security: Models, Methods, and Metrics

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Security Advantages and Challenges of 3D Heterogeneous Integration

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Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead

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2.5D/3D Integration Technologies for Circuit Obfuscation

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A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits

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Exploiting hardware obfuscation methods to prevent and detect hardware Trojans

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A hardware obfuscation technique for manufacturing a secure 3D IC

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Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis

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Co-Design for Heterogeneous Integration: High Level Decisions to the Rescue

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Combined Split Manufacturing and Logic Obfuscation Based on Emerging Technologies at High Level for Secure 3D IC Design

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Configurable Inter-Tier Connectivity for Secure 3D IC Design

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Tracking Cloned Electronic Components using a Consortium-based Blockchain Infrastructure

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Analyzing Area and Latency Overhead in C and RTL Locked Designs

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A2: Analog Malicious Hardware

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Hardening Circuit-Design IP Against Reverse-Engineering Attacks

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A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion

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Obfuscated Built-In Self-Authentication With Secure and Efficient Wire-Lifting

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Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

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TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing

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Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure

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Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications

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Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation

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Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing

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A Neural Network-Based Cognitive Obfuscation Toward Enhanced Logic Locking

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Optimizing the Use of Behavioral Locking for High-Level Synthesis

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HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language

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A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs

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THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

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A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis

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A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

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Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices

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On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes

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Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing

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X-DFS: Explainable Artificial Intelligence Guided Design-for-Security Solution Space Exploration

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Security and Vulnerability Implications of 3D ICs

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Secure Integrated Circuit Design via Hybrid Cloud

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Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits?

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The Cat and Mouse in Split Manufacturing

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Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

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An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies

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Analysis of Security of Split Manufacturing Using Machine Learning

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ASSURE: RTL Locking Against an Untrusted Foundry

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Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning

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Protecting Analog Circuits Using Switch Mode Time Domain Locking

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Effect of split manufacturing on power supply requirements

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On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits

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Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities

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Modeling and test generation for combinational hardware Trojans

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Special Session: Novel Attacks on Logic-Locking

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LEAD: Link Exploitability Analysis for Die-to-Die Interconnects in Heterogeneous Integration *

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Raise your game for split manufacturing

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Layout recognition attacks on split manufacturing

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Hardware Security For and Beyond CMOS Technology

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ObfusX

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Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures

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Hardware Security for and beyond CMOS Technology

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Predictive Model Attack for Embedded FPGA Logic Locking

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A Noninvasive Technique to Detect Authentic/Counterfeit SRAM Chips

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An IP-Agnostic Foundational Cell Array Offering Supply Chain Security

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Security Aware Placement for Split Manufactured Integrated Circuit Design Flows

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Graph Neural Networks for Integrated Circuit Design, Reliability, and Security: Survey and Tool

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

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Physical Unclonable Functions based Hardware Obfuscation Techniques: A State of the Art

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A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL

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A Cognitive SAT to SAT-Hard Clause Translation-based Logic Obfuscation

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Hardware Trojans in eNVM Neuromorphic Devices

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Programmable EM Sensor Array for Golden-Model Free Run-Time Trojan Detection and Localization

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The Decomposition and Combination Paradigms of Chiplet-Based Integrated Chips

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Improving the Physical Security of Microchips against Side-Channel Attacks

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Improving the Physical Security of Microchip

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A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL

inferred← citeshttps://doi.org/10.3390/electronics4030541openalex-snapshot

Beyond the Interconnections: Split Manufacturing in RF Designs

inferred← citeshttps://doi.org/10.3390/electronics4040763openalex-snapshot

Introduction to Hardware Security

inferred← citeshttps://doi.org/10.3390/electronics6030067openalex-snapshot

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

inferred← citeshttps://doi.org/10.4071/001c.74768openalex-snapshot

Reconfigurable NEMS based Advance Packaging for Anti Reverse Engineering and Counterfeiting

inferred← citeshttps://doi.org/10.70675/7c887878z5a2fz44c9z979az1d7fcc339b6aopenalex-snapshot

Design for security in mixed analog-digital integrated circuits

inferred← citeshttps://doi.org/10.70675/f39bef5ez15c6z462dzb62azf0b2da5898ceopenalex-snapshot

Conception de matériel salutaire pour lutter contre la contrefaçon et le vol de circuits intégrés

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