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Introduction to Hardware Security
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11894063_21openalex-snapshot
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
inferredcites →https://doi.org/10.1007/3-540-36400-5openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2002
inferredcites →https://doi.org/10.1007/3-540-44709-1_21openalex-snapshot
Electromagnetic Analysis: Concrete Results
inferredcites →https://doi.org/10.1007/3-540-45418-7_17openalex-snapshot
ElectroMagnetic Analysis (EMA): Measures and Counter-measures for Smart Cards
inferredcites →https://doi.org/10.1007/3-540-68697-5_9openalex-snapshot
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
inferredcites →https://doi.org/10.1007/978-1-4419-8080-9openalex-snapshot
Introduction to Hardware Security and Trust
inferredcites →https://doi.org/10.1007/978-1-4419-8080-9_4openalex-snapshot
Security Based on Physical Unclonability and Disorder
inferredcites →https://doi.org/10.1007/978-3-540-24660-2_18openalex-snapshot
Hardware Countermeasures against DPA – A Statistical Analysis of Their Effectiveness
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_25openalex-snapshot
Efficient Countermeasures against RPA, DPA, and SPA
inferredcites →https://doi.org/10.1007/978-3-540-87403-4_1openalex-snapshot
Guest-Transparent Prevention of Kernel Rootkits with VMM-Based Memory Shadowing
inferredcites →https://doi.org/10.1007/978-3-642-04138-9_27openalex-snapshot
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering
inferredcites →https://doi.org/10.1007/978-3-642-04138-9_28openalex-snapshot
MERO: A Statistical Approach for Hardware Trojan Detection
inferredcites →https://doi.org/10.1007/978-3-642-04431-1_16openalex-snapshot
SVD-Based Ghost Circuitry Detection
inferredcites →https://doi.org/10.1007/978-3-642-15031-9_23openalex-snapshot
An Alternative to Error Correction for SRAM-Like PUFs
inferredcites →https://doi.org/10.1007/978-3-642-23951-9openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28 - October 1, 2011. Proceedings
inferredcites →https://doi.org/10.1007/978-3-642-29912-4_8openalex-snapshot
A New Scan Attack on RSA in Presence of Industrial Countermeasures
inferredcites →https://doi.org/10.1007/978-3-642-40349-1_12openalex-snapshot
Stealthy Dopant-Level Hardware Trojans
inferredcites →https://doi.org/10.1016/j.comnet.2005.01.010openalex-snapshot
Remote timing attacks are practical
inferredcites →https://doi.org/10.1016/j.cose.2009.03.002openalex-snapshot
Providing secure execution environments with a last line of defense against Trojan circuit attacks
inferredcites →https://doi.org/10.1016/j.scico.2004.01.003openalex-snapshot
Building certified libraries for PCC: dynamic storage allocation
inferredcites →https://doi.org/10.1023/b:jars.0000021012.97318.e9openalex-snapshot
A Syntactic Approach to Foundational Proof-Carrying Code
inferredcites →https://doi.org/10.1109/async.2002.1000311openalex-snapshot
Improving smart card security using self-timed circuits
inferredcites →https://doi.org/10.1109/ats.2014.69openalex-snapshot
Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs
inferredcites →https://doi.org/10.1109/date.2006.244019openalex-snapshot
A secure Scan Design Methodology
inferredcites →https://doi.org/10.1109/date.2008.4484823openalex-snapshot
EPIC: Ending Piracy of Integrated Circuits
inferredcites →https://doi.org/10.1109/date.2012.6176634openalex-snapshot
Logic encryption: A fault analysis perspective
inferredcites →https://doi.org/10.1109/dft.2012.6378191openalex-snapshot
Parametric counterfeit IC detection via Support Vector Machines
inferredcites →https://doi.org/10.1109/dft.2012.6378192openalex-snapshot
Path-delay fingerprinting for identification of recovered ICs
inferredcites →https://doi.org/10.1109/ets.2013.6569368openalex-snapshot
Reconciling the IC test and security dichotomy
inferredcites →https://doi.org/10.1109/fits.2003.1264926openalex-snapshot
Foundational proof-carrying code
inferredcites →https://doi.org/10.1109/fpl.2010.59openalex-snapshot
Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic Reconfiguration
inferredcites →https://doi.org/10.1109/hpca.2010.5416657openalex-snapshot
Scalable architectural support for trusted software
inferredcites →https://doi.org/10.1109/hst.2008.4559037openalex-snapshot
Sensitivity analysis to hardware Trojans using power supply transient signals
inferredcites →https://doi.org/10.1109/hst.2008.4559049openalex-snapshot
Hardware Trojan detection using path delay fingerprint
inferredcites →https://doi.org/10.1109/hst.2009.5224959openalex-snapshot
OS support for detecting Trojan circuit attacks
inferredcites →https://doi.org/10.1109/hst.2009.5224960openalex-snapshot
VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs
inferredcites →https://doi.org/10.1109/hst.2009.5224968openalex-snapshot
New design strategy for improving hardware Trojan detection and reducing Trojan activation time
inferredcites →https://doi.org/10.1109/hst.2009.5224971openalex-snapshot
Experiences in Hardware Trojan design and implementation
inferredcites →https://doi.org/10.1109/hst.2010.5513114openalex-snapshot
Trusted RTL: Trojan detection methodology in pre-silicon designs
inferredcites →https://doi.org/10.1109/hst.2011.5954988openalex-snapshot
Enhancing security via provably trustworthy hardware intellectual property
inferredcites →https://doi.org/10.1109/hst.2011.5954998openalex-snapshot
Case study: Detecting hardware Trojans in third-party digital IP cores
inferredcites →https://doi.org/10.1109/hst.2013.6581573openalex-snapshot
Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing
inferredcites →https://doi.org/10.1109/hst.2013.6581574openalex-snapshot
On hardware Trojan design and implementation at register-transfer level
inferredcites →https://doi.org/10.1109/hst.2014.6855560openalex-snapshot
Split-fabrication obfuscation: Metrics and techniques
inferredcites →https://doi.org/10.1109/hst.2014.6855587openalex-snapshot
DWM-PUF: A low-overhead, memory-based security primitive
inferredcites →https://doi.org/10.1109/iccad.2008.4681643openalex-snapshot
Power supply signal calibration techniques for improving detection resolution to hardware Trojans
inferredcites →https://doi.org/10.1109/iccad.2013.6691149openalex-snapshot
Hardware Trojans in wireless cryptographic ICs: Silicon demonstration & detection method evaluation
inferredcites →https://doi.org/10.1109/iccad.2013.6691208openalex-snapshot
A proof-carrying based framework for trusted microprocessor IP
inferredcites →https://doi.org/10.1109/iccad.2014.7001345openalex-snapshot
A non-volatile memory based physically unclonable function without helper data
inferredcites →https://doi.org/10.1109/iccad.2014.7001362openalex-snapshot
Hardware obfuscation using PUF-based logic
inferredcites →https://doi.org/10.1109/iccd.2011.6081410openalex-snapshot
Blue team red team approach to hardware trust assessment
inferredcites →https://doi.org/10.1109/icecs.2010.5724725openalex-snapshot
DFTT: Design for Trojan Test
inferredcites →https://doi.org/10.1109/isias.2010.5604061openalex-snapshot
Fault attack on AES with single-bit induced faults
inferredcites →https://doi.org/10.1109/isscc.2012.6177067openalex-snapshot
Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory
inferredcites →https://doi.org/10.1109/isvlsi.2012.40openalex-snapshot
Nano-PPUF: A Memristor-Based Security Primitive
inferredcites →https://doi.org/10.1109/isvlsi.2014.54openalex-snapshot
Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits
inferredcites →https://doi.org/10.1109/mc.2010.284openalex-snapshot
Ending Piracy of Integrated Circuits
inferredcites →https://doi.org/10.1109/mc.2010.299openalex-snapshot
Trustworthy Hardware: Identifying and Classifying Hardware Trojans
inferredcites →https://doi.org/10.1109/mdt.2010.21openalex-snapshot
Hardware Trojans in Wireless Cryptographic ICs
inferredcites →https://doi.org/10.1109/mdt.2010.25openalex-snapshot
Secure and robust error correction for physical unclonable functions
inferredcites →https://doi.org/10.1109/mdt.2010.7openalex-snapshot
A Survey of Hardware Trojan Taxonomy and Detection
inferredcites →https://doi.org/10.1109/nano.2014.6968027openalex-snapshot
A novel geometry based MRAM PUF
inferredcites →https://doi.org/10.1109/reconfig.2009.31openalex-snapshot
Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules
inferredcites →https://doi.org/10.1109/recosoc.2011.5981499openalex-snapshot
Achieving hardware security for reconfigurable systems on chip by a proof-carrying code approach
inferredcites →https://doi.org/10.1109/sp.2007.36openalex-snapshot
Trojan Detection using IC Fingerprinting
inferredcites →https://doi.org/10.1109/sp.2010.18openalex-snapshot
Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically
inferredcites →https://doi.org/10.1109/sp.2011.32openalex-snapshot
Defeating UCI: Building Stealthy and Malicious Hardware
inferredcites →https://doi.org/10.1109/tc.2013.193openalex-snapshot
Fault Analysis-Based Logic Encryption
inferredcites →https://doi.org/10.1109/tcad.2005.862745openalex-snapshot
Secure Scan: A Design-for-Test Architecture for Crypto Chips
inferredcites →https://doi.org/10.1109/tcad.2007.906483openalex-snapshot
Secured Flipped Scan-Chain Model for Crypto-Architecture
inferredcites →https://doi.org/10.1109/tcad.2014.2366876openalex-snapshot
Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor
inferredcites →https://doi.org/10.1109/tdsc.2007.70215openalex-snapshot
Securing Designs against Scan-Based Side-Channel Attacks
inferredcites →https://doi.org/10.1109/test.2004.1386969openalex-snapshot
Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard
inferredcites →https://doi.org/10.1109/tifs.2011.2136339openalex-snapshot
An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities
inferredcites →https://doi.org/10.1109/tifs.2011.2160627openalex-snapshot
Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition
inferredcites →https://doi.org/10.1109/tifs.2013.2279798openalex-snapshot
PUF Modeling Attacks on Simulated and Silicon Data
inferredcites →https://doi.org/10.1109/vlsi.design.2009.22openalex-snapshot
A Novel Sustained Vector Technique for the Detection of Hardware Trojans
inferredcites →https://doi.org/10.1109/vts.2007.89openalex-snapshot
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips
inferredcites →https://doi.org/10.1109/vts.2012.6231061openalex-snapshot
Are advanced DfT structures sufficient for preventing scan-attacks?
inferredcites →https://doi.org/10.1109/vts.2012.6231062openalex-snapshot
Proof carrying-based information flow tracking for data secrecy protection and hardware trust
inferredcites →https://doi.org/10.1109/wifs.2012.6412622openalex-snapshot
Machine learning attacks on 65nm Arbiter PUFs: Accurate modeling poses strict bounds on usability
inferredcites →https://doi.org/10.1145/1080695.1069971openalex-snapshot
Architecture for Protecting Critical Secrets in Microprocessors
inferredcites →https://doi.org/10.1145/1133255.1134028openalex-snapshot
Modular verification of assembly code with stack-based control abstractions
inferredcites →https://doi.org/10.1145/1278480.1278484openalex-snapshot
Physical unclonable functions for device authentication and secret key generation
inferredcites →https://doi.org/10.1145/1315245.1315262openalex-snapshot
Stealthy malware detection through vmm-based "out-of-the-box" semantic view reconstruction
inferredcites →https://doi.org/10.1145/1346281.2181012openalex-snapshot
Designing and implementing malicious processors
inferredcites →https://doi.org/10.1145/1366110.1366196openalex-snapshot
Guided test generation for isolation and detection of embedded trojans in ics
inferredcites →https://doi.org/10.1145/1403375.1403703openalex-snapshot
Towards trojan-free trusted ICs
inferredcites →https://doi.org/10.1145/1629911.1630091openalex-snapshot
Hardware Trojan horse detection using gate-level characterization
inferredcites →https://doi.org/10.1145/1866307.1866335openalex-snapshot
Modeling attacks on physical unclonable functions
inferredcites →https://doi.org/10.1145/2024724.2024947openalex-snapshot
Power-gated MOS current mode logic (PG-MCML)
inferredcites →https://doi.org/10.1145/2150976.2151022openalex-snapshot
Architectural support for hypervisor-secure virtualization
inferredcites →https://doi.org/10.1145/2248487.2151022openalex-snapshot
Architectural support for hypervisor-secure virtualization
inferredcites →https://doi.org/10.1145/2459976.2459985openalex-snapshot
Interlocking obfuscation for anti-tamper hardware
inferredcites →https://doi.org/10.1145/2487726.2488368openalex-snapshot
Innovative instructions and software model for isolated execution
inferredcites →https://doi.org/10.1145/2508859.2516656openalex-snapshot
Security analysis of integrated circuit camouflaging
inferredcites →https://doi.org/10.1145/2593069.2593123openalex-snapshot
Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack
inferredcites →https://doi.org/10.1145/2670967.2670969openalex-snapshot
Hardware-software collaboration for secure coexistence with kernel extensions
inferredcites →https://doi.org/10.1145/2744769.2747939openalex-snapshot
Pre-silicon security verification and validation
inferredcites →https://doi.org/10.1145/356989.357005openalex-snapshot
Architectural support for copy and tamper resistant software
inferredcites →https://doi.org/10.1145/378995.379237openalex-snapshot
Architectural support for copy and tamper resistant software
inferredcites →https://doi.org/10.1145/504709.504712openalex-snapshot
An indexed model of recursive types for foundational proof-carrying code
inferredcites →https://doi.org/10.1155/2010/180242openalex-snapshot
Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification
inferredcites →https://doi.org/10.3390/electronics4030541openalex-snapshot
Beyond the Interconnections: Split Manufacturing in RF Designs
inferredcites →https://doi.org/10.48456/tr-858openalex-snapshot
CHERI: A RISC capability machine for practical memory safety
inferredcites →https://doi.org/10.5555/1509456.1509596openalex-snapshot
Power supply signal calibration techniques for improving detection resolution to hardware Trojans
inferredcites →https://doi.org/10.5555/1899721.1899821openalex-snapshot
Scan-based attack against elliptic curve cryptosystems
inferredcites →https://doi.org/10.5555/2485288.2485591openalex-snapshot
Is split manufacturing secure
inferredcites →https://doi.org/10.5555/2492708.2492947openalex-snapshot
Logic encryption: a fault analysis perspective
inferredcites →https://doi.org/10.5555/2492708.2492949openalex-snapshot
Post-deployment trust evaluation in wireless cryptographic ICs
inferredcites →https://doi.org/10.5555/2492708.2493035openalex-snapshot
A sensor-assisted self-authentication framework for hardware trojan detection
inferredcites →https://doi.org/10.5555/2561828.2561908openalex-snapshot
Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation
inferredcites →https://doi.org/10.5555/2561828.2561986openalex-snapshot
A proof-carrying based framework for trusted microprocessor IP
inferredcites →https://doi.org/10.5555/2616606.2616718openalex-snapshot
Real-time trust evaluation in integrated circuits
inferredcites →https://doi.org/10.7873/date2014.104openalex-snapshot
Real-time trust evaluation in integrated circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Stimulus‐Gated Neuromorphic Watermarking With 2D Siloxene‐Based UV Synaptic Phototransistors for Next‐Generation IC Security
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Ternary Computing to Strengthen Cybersecurity
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Response-Based Cryptographic Methods with Ternary Physical Unclonable Functions
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Password Manager Combining Hashing Functions and Ternary PUFs
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IC Camouflaging Optimization and Evaluation
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Statistical Analysis to Optimize the Generation of Cryptographic Keys from Physical Unclonable Functions
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Hardware Security in Evolving FinTech Landscape
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A ReRAM Physically Unclonable Function (ReRAM PUF)-Based Approach to Enhance Authentication Security in Software Defined Wireless Networks
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Hardware Obfuscation for IP Protection of DSP Applications
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Hardware Trojans Detection and Prevention Techniques Review
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Spear and Shield: Evolution of Integrated Circuit Camouflaging
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Key Update Countermeasure for Correlation-Based Side-Channel Attacks
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Theorem proof based gate level information flow tracking for hardware security verification
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True random number generators in modern cryptography: A review
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Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding
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Secure Electronics Enabled by Atomically Thin and Photosensitive Two-Dimensional Memtransistors
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Decision model with quantification of buyer-supplier trust in advanced technology enterprises
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A conflict-free approach for parallelizing SAT-based de-camouflaging attacks
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Evaluation and Comparison of Physical Unclonable Functions suitable for FPGA Implementation
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Bit selection algorithm suitable for high-volume production of SRAM-PUF
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Delay based Physical Unclonable Function for Hardware Security and Trust
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Property Based Formal Security Verification for Hardware Trojan Detection
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Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters
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Novel technique to improve strength of weak arbiter PUF
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A Proof of Concept SRAM-based Physically Unclonable Function (PUF) Key Generation Mechanism for IoT Devices
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A XOR data compiler: Combined with physical unclonable function for true random number generation
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Provably Secure Camouflaging Strategy for IC Protection
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Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis
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Golden-Chip-Free Hardware Trojan Detection Through Quiescent Thermal Maps
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PUF designed with Resistive RAM and Ternary States
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Provably secure camouflaging strategy for IC protection
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How Secure Is Split Manufacturing in Preventing Hardware Trojan?
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Hardware Security in Spin-based Computing-in-memory
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Golden Chip-Free Trojan Detection Leveraging Trojan Trigger’s Side-Channel Fingerprinting
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ZSafe: Proving the Safety of Proprietary Hardware Designs in Zero Knowledge
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Adaptive key generation algorithm based on software engineering methodology
inferred← citeshttps://doi.org/10.1587/essfr.8.177openalex-snapshot
IC Chip Authentication and Guarantee
inferred← citeshttps://doi.org/10.21533/pen.v6.i2.1720openalex-snapshot
METAPUF A Challenge Response Pair Generator
inferred← citeshttps://doi.org/10.22360/springsim.2019.cns.004openalex-snapshot
Unequally Powered Cryptography with Physical Unclonable Functions for Networks of Internet of Things Terminals
inferred← citeshttps://doi.org/10.23919/springsim.2019.8732853openalex-snapshot
Unequally Powered Cryptography With Physical Unclonable Functions for Networks of Internet of Things Terminals
inferred← citeshttps://doi.org/10.25046/aj030303openalex-snapshot
Design of True Random Numbers Generators with Ternary Physical Unclonable Functions
inferred← citeshttps://doi.org/10.3389/frcmn.2025.1443592openalex-snapshot
Enhancing security of mobile crowd sensing in unmanned aerial vehicle ecosystems
inferred← citeshttps://doi.org/10.3390/app12041785openalex-snapshot
Key Recovery for Content Protection Using Ternary PUFs Designed with Pre-Formed ReRAM
inferred← citeshttps://doi.org/10.3390/cryptography2010006openalex-snapshot
Can Ternary Computing Improve Information Assurance?
inferred← citeshttps://doi.org/10.3390/cryptography4020017openalex-snapshot
Securing Additive Manufacturing with Blockchains and Distributed Physically Unclonable Functions
inferred← citeshttps://doi.org/10.3390/electronics10111256openalex-snapshot
Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit
inferred← citeshttps://doi.org/10.3390/electronics8060623openalex-snapshot
A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology
inferred← citeshttps://doi.org/10.3390/fi17040175openalex-snapshot
A Survey on Edge Computing (EC) Security Challenges: Classification, Threats, and Mitigation Strategies
inferred← citeshttps://doi.org/10.3390/info15040173openalex-snapshot
A Quantum-Safe Software-Defined Deterministic Internet of Things (IoT) with Hardware-Enforced Cyber-Security for Critical Infrastructures
inferred← citeshttps://doi.org/10.3390/s21010028openalex-snapshot
Proof-of-PUF Enabled Blockchain: Concurrent Data and Device Security for Internet-of-Energy
inferred← citeshttps://doi.org/10.4018/979-8-3373-9983-6.ch004openalex-snapshot
Systematic Review on Machine Learning Applications in Hardware Security for Vehicles
inferred← citeshttps://doi.org/10.48550/arxiv.2006.01425openalex-snapshot
Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques
inferred← citeshttps://doi.org/10.48550/arxiv.2107.04175openalex-snapshot
A Survey on RISC-V Security: Hardware and Architecture
inferred← citeshttps://doi.org/10.5555/3201607.3201661openalex-snapshot
A conflict-free approach for parallelizing SAT-based de-camouflaging attacks
inferred← citeshttps://doi.org/10.7176/ceis/12-2-01openalex-snapshot
A Survey on Integrated Circuit Trojans
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