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A Transparent and Energy Aware Reconfigurable Multiprocessor Platform for Simultaneous ILP and TLP Exploitation

https://doi.org/10.7873/date.2013.317

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inferred← citeshttps://doi.org/10.1007/978-3-319-30481-6_21openalex-snapshot

Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System

inferred← citeshttps://doi.org/10.1007/s10617-021-09258-6openalex-snapshot

An energy efficient multi-target binary translator for instruction and data level parallelism exploitation

inferred← citeshttps://doi.org/10.1007/s11227-025-07131-yopenalex-snapshot

AccPRET: a proposal of a multicore architecture with reconfigurable accelerators and time predictability

inferred← citeshttps://doi.org/10.1109/iscas.2017.8050438openalex-snapshot

A framework to automatically generate heterogeneous organization reconfigurable multiprocessing

inferred← citeshttps://doi.org/10.1109/isvlsi.2016.67openalex-snapshot

The Impact of Heterogeneity on a Reconfigurable Multicore System

inferred← citeshttps://doi.org/10.1109/sbcci50935.2020.9189927openalex-snapshot

A Management Technique for Concurrent Access to a Reconfigurable Accelerator

inferred← citeshttps://doi.org/10.1109/sbesc.2014.21openalex-snapshot

Towards a Dynamic and Reconfigurable Multicore Heterogeneous System

inferred← citeshttps://doi.org/10.1109/sbesc.2018.00044openalex-snapshot

A Coarse-Grained Reconfigurable Architecture for a PRET Machine

inferred← citeshttps://doi.org/10.1145/3369764openalex-snapshot

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

inferred← citeshttps://doi.org/10.23919/date.2019.8715121openalex-snapshot

TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration

inferred← citeshttps://doi.org/10.7873/date.2013.013openalex-snapshot

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