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Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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The MOLEN ρμ-Coded Processor
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The superblock: An effective technique for VLIW and superscalar compilation
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An architecture framework for an adaptive extensible processor
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Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization
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ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism
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Customizing VLIW processors from dynamically profiled execution traces
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Towards a multiple-ISA embedded system
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MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
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Dynamic binary translation and optimization
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Welcome to the opportunities of binary translation
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Dynamic and transparent binary translation
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UQBT: adaptable binary translation at low cost
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Dynamic Translation Optimization Method Based on Static Pre-Translation
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Proceedings Design, Automation and Test in Europe Conference and Exhibition
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A configurable logic architecture for dynamic hardware/software partitioning
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Exploiting Memory-Level Parallelism in Reconfigurable Accelerators
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Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
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From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
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Efficient data-stream management for shared-memory many-core systems
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Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays
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Proceedings 2007 International Conference on Field Programmable Technology
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Bridging the computation gap between programmable processors and hardwired accelerators
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Dynamically Specialized Datapaths for energy efficient computing
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A Just-in-Time Customizable processor
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CUDA Compatible GPU as an Efficient Hardware Accelerator for AES Cryptography
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PipeRench: a coprocessor for streaming multimedia acceleration
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An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
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VEAL: Virtualized Execution Accelerator for Loops
inferredcites →https://doi.org/10.1109/isocc.2011.6138785openalex-snapshot
A host-accelerator communication architecture design for efficient binary acceleration
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Hardware/Software Codesign: The Past, the Present, and Predicting the Future
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Efficient Processing of Deep Neural Networks: A Tutorial and Survey
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Design of ion-implanted MOSFET's with very small physical dimensions
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A decade of hardware/ software codesign
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Warp Processing: Dynamic Translation of Binaries to FPGA Circuits
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OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems
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Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
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Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization
inferredcites →https://doi.org/10.1109/mm.2012.17openalex-snapshot
Dark Silicon and the End of Multicore Scaling
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DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing
inferredcites →https://doi.org/10.1109/mm.2013.90openalex-snapshot
A Landscape of the New Dark Silicon Design Regime
inferredcites →https://doi.org/10.1109/pacrim.2009.5291237openalex-snapshot
Coarse-grain reconfigurable architectures - taxonomy -
inferredcites →https://doi.org/10.1109/samos.2014.6893197openalex-snapshot
A run-time modulo scheduling by using a binary translation mechanism
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Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware
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Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays
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Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW
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Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces
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Dynamic Partial Reconfiguration of Customized Single-Row Accelerators
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An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
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Modulo scheduling for highly customized datapaths to increase hardware reusability
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Scalable Parallel Programming with CUDA
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Design and implementation of a MicroBlaze-based warp processor
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Accelerating SQL database operations on a GPU with CUDA
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Binary acceleration using coarse-grained reconfigurable architecture
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The Instruction-Set Extension Problem
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Clock Tree synthesis for TSV-based 3D IC designs
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Bundled execution of recurring traces for energy-efficient general purpose processing
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Power Limitations and Dark Silicon Challenge the Future of Multicore
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Architectures of flexible symmetric key crypto engines—a survey
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A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
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Optimizing Indirect Branches in Dynamic Binary Translators
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A Survey of Mobile Device Virtualization
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Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design
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Coarse grain reconfigurable architecture (embedded tutorial)
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Software pipelining: an effective scheduling technique for VLIW machines
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Characterizing embedded applications for instruction-set extensible processors
inferredcites →https://doi.org/10.1155/2011/546962openalex-snapshot
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment
inferredcites →https://doi.org/10.2197/ipsjtsldm.4.31openalex-snapshot
Coarse-Grained Reconfigurable Array: Architecture and Application Mapping
inferredcites →https://doi.org/10.23919/date.2017.7927147openalex-snapshot
Hardware-accelerated dynamic binary translation
inferredcites →https://doi.org/10.4018/978-1-61350-116-0openalex-snapshot
Handbook of Research on Computational Science and Engineering: Theory and Practice
inferredcites →https://doi.org/10.7873/date.2013.317openalex-snapshot
A Transparent and Energy Aware Reconfigurable Multiprocessor Platform for Simultaneous ILP and TLP Exploitation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA
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Performance assessment of the metaheuristic optimization algorithms: an exhaustive review
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Software/Hardware Co-Verification for Custom Instruction Set Processors
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Automatic Compilation of CNN on Reconfigurable Array Processor Based on Scalable Instruction Group Library
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Design Space Exploration of HW Accelerators and Network Infrastructure for FPGA-Based MPSoC
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Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework
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Invited Paper: Instruction Set Extensions for Post-Quantum Cryptography
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On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators
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Energy-Efficient Mappings in the Athena CGRA
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Trends and Challenges in Ensuring Security for Low-Power and High-Performance Embedded SoCs
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A Binary Translation Framework for Automated Hardware Generation
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RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V
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Wireless Powered Mobile Edge Computing Networks: A Survey
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Landscape of High-Performance Python to Develop Data Science and Machine Learning Applications
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GreenCompile: A Comparative Energy Analysis of Cross Platform Compiler EfficiencyAcross Modern CPU Architectures
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Research on Storage Structure Design and Performance Optimization Strategy of Embedded System for Low-Capacity Storage Units
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