On the public citation graph
40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS
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What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-51724-7_12openalex-snapshot
Distributed In-Memory Computing on Binary Memristor-Crossbar for Machine Learning
inferred← citeshttps://doi.org/10.1007/s11227-018-2339-0openalex-snapshot
A joint optimization method for NoC topology generation
inferred← citeshttps://doi.org/10.1016/j.mejo.2013.12.008openalex-snapshot
Nanoelectronic SET-based core for network-on-chip architectures
inferred← citeshttps://doi.org/10.1080/03772063.2018.1534618openalex-snapshot
High-Speed On-Chip Signaling: Voltage or Current-Mode?
inferred← citeshttps://doi.org/10.1109/aspdac.2016.7428024openalex-snapshot
An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar
inferred← citeshttps://doi.org/10.1109/asscc.2016.7844155openalex-snapshot
A 5.1Gb/s 60.3fJ/bit/mm PVT tolerant NoC transceiver
inferred← citeshttps://doi.org/10.1109/jssc.2021.3095343openalex-snapshot
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications
inferred← citeshttps://doi.org/10.1109/mdts58049.2023.10168152openalex-snapshot
Effect of Resistance variability in Vector Matrix Multiplication operations of 1T1R ReRAM crossbar arrays using an Embedded test platform
inferred← citeshttps://doi.org/10.1109/micro.2014.19openalex-snapshot
Dodec: Random-Link, Low-Radix On-Chip Networks
inferred← citeshttps://doi.org/10.1109/tc.2015.2439255openalex-snapshot
A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and Memory
inferred← citeshttps://doi.org/10.1109/tc.2021.3073255openalex-snapshot
Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification
inferred← citeshttps://doi.org/10.1109/tnano.2015.2447531openalex-snapshot
An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices
inferred← citeshttps://doi.org/10.1145/2996192openalex-snapshot
Distributed In-Memory Computing on Binary RRAM Crossbar
inferred← citeshttps://doi.org/10.1145/3225058.3225118openalex-snapshot
Click-Based Asynchronous Mesh Network with Bounded Bundled Data
inferred← citeshttps://doi.org/10.2200/s00736ed1v01y201609eet008openalex-snapshot
Non-Volatile In-Memory Computing by Spintronics
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.32657/10356/62147openalex-snapshot
Non-volatile in-memory computing
inferred← citeshttps://doi.org/10.32657/10356/65486openalex-snapshot
2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip
inferred← citeshttps://doi.org/10.32657/10356/73177openalex-snapshot
In-memory computing by RRAM for machine learning
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