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Dodec: Random-Link, Low-Radix On-Chip Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Genetic Algorithms and grouping problems
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Modeling and evaluation of ring-based interconnects for Network-on-Chip
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Express cubes: improving the performance of k-ary n-cube interconnection networks
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A new theory of deadlock-free adaptive routing in wormhole networks
inferredcites →https://doi.org/10.1109/71.334898openalex-snapshot
Adaptive deadlock- and livelock-free routing with all minimal paths in torus networks
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A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks
inferredcites →https://doi.org/10.1109/asscc.2010.5716540openalex-snapshot
A 48-core IA-32 processor with on-die message-passing and DVFS in 45nm CMOS
inferredcites →https://doi.org/10.1109/fpl.2013.6645496openalex-snapshot
The power of communication: Energy-efficient NOCS for FPGAS
inferredcites →https://doi.org/10.1109/hipc.1997.634511openalex-snapshot
Improving the efficiency of adaptive routing in networks with irregular topology
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/hpca.2009.4798234openalex-snapshot
A low-radix and low-diameter 3D interconnection network design
inferredcites →https://doi.org/10.1109/hpca.2009.4798251openalex-snapshot
Express Cube Topologies for on-Chip Interconnects
inferredcites →https://doi.org/10.1109/iiswc.2009.5306792openalex-snapshot
A communication characterisation of Splash-2 and Parsec
inferredcites →https://doi.org/10.1109/isca.2005.35openalex-snapshot
Microarchitecture of a High-Radix Router
inferredcites →https://doi.org/10.1109/isca.2012.6237016openalex-snapshot
A case for random shortcut topologies for HPC interconnects
inferredcites →https://doi.org/10.1109/ispass.2013.6557149openalex-snapshot
A detailed and flexible cycle-accurate Network-on-Chip simulator
inferredcites →https://doi.org/10.1109/isscc.2007.373606openalex-snapshot
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
inferredcites →https://doi.org/10.1109/issoc.2004.1411133openalex-snapshot
Spidergon: a novel on-chip communication network
inferredcites →https://doi.org/10.1109/jssc.2010.2079450openalex-snapshot
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
inferredcites →https://doi.org/10.1109/micro.2003.1253187openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferredcites →https://doi.org/10.1109/micro.2007.29openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferredcites →https://doi.org/10.1109/micro.2010.18openalex-snapshot
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
inferredcites →https://doi.org/10.1109/mm.2007.4378780openalex-snapshot
On-Chip Interconnection Architecture of the Tile Processor
inferredcites →https://doi.org/10.1109/nocs.2010.27openalex-snapshot
Design of High-Radix Clos Network-on-Chip
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/tc.1987.1676910openalex-snapshot
Evaluation of On-Chip Static Interconnection Networks
inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1109/tvlsi.2006.878263openalex-snapshot
"It's a small world after all": NoC performance optimization via long-range link insertion
inferredcites →https://doi.org/10.1145/1080695.1070005openalex-snapshot
Microarchitecture of a High-Radix Router
inferredcites →https://doi.org/10.1145/1080695.1070006openalex-snapshot
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
inferredcites →https://doi.org/10.1145/1183401.1183430openalex-snapshot
Design tradeoffs for tiled CMP on-chip networks
inferredcites →https://doi.org/10.1145/1250662.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferredcites →https://doi.org/10.1145/1555754.1555782openalex-snapshot
Application-aware deadlock-free oblivious routing
inferredcites →https://doi.org/10.1145/1555754.1555810openalex-snapshot
Achieving predictable performance through better memory controller placement in many-core CMPs
inferredcites →https://doi.org/10.1145/1645213.1645217openalex-snapshot
Router microarchitecture and scalability of ring topology in on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669151openalex-snapshot
A case for dynamic frequency tuning in on-chip networks
inferredcites →https://doi.org/10.1145/215399.215455openalex-snapshot
ROMM routing on mesh and torus networks
inferredcites →https://doi.org/10.1145/2366231.2337179openalex-snapshot
A case for random shortcut topologies for HPC interconnects
inferredcites →https://doi.org/10.1145/3749740.3749751openalex-snapshot
Universal Schemes for Parallel Communication
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.7873/date.2013.332openalex-snapshot
40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-49583-5_23openalex-snapshot
Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length
inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.001openalex-snapshot
Dark Silicon and the History of Computing
inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.009openalex-snapshot
Topology Specialization for Networks-on-Chip in the Dark Silicon Era
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.03.004openalex-snapshot
Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology
inferred← citeshttps://doi.org/10.1109/cads.2017.8310674openalex-snapshot
NOC characteristics of cloud applications
inferred← citeshttps://doi.org/10.1109/hpca.2017.16openalex-snapshot
Near-Ideal Networks-on-Chip for Servers
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00044openalex-snapshot
DRAIN: Deadlock Removal for Arbitrary Irregular Networks
inferred← citeshttps://doi.org/10.1109/icpads.2017.00091openalex-snapshot
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies
inferred← citeshttps://doi.org/10.1109/icpp.2016.46openalex-snapshot
Randomly Optimized Grid Graph for Low-Latency Interconnection Networks
inferred← citeshttps://doi.org/10.1109/igcc.2015.7393734openalex-snapshot
A high-density data path implementation fitting for HTC applications
inferred← citeshttps://doi.org/10.1109/iintec.2017.8325926openalex-snapshot
Phosphorus: An ultra low footprint and energy consumption 3D NoC architecture
inferred← citeshttps://doi.org/10.1109/pdp.2016.18openalex-snapshot
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication
inferred← citeshttps://doi.org/10.1587/transinf.2018edp7367openalex-snapshot
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.48550/arxiv.2010.10683openalex-snapshot
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
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