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Fast and Precise Cache Performance Estimation for Out-Of-Order Execution

https://doi.org/10.7873/date.2015.0066
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inferred← citeshttps://doi.org/10.1016/j.micpro.2017.02.005openalex-snapshot
An artificial neural network model of LRU-cache misses on out-of-order embedded processors
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.10.001openalex-snapshot
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.07.004openalex-snapshot
Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures
inferred← citeshttps://doi.org/10.1109/fdl63219.2024.10673859openalex-snapshot
An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs
inferred← citeshttps://doi.org/10.1109/pacrim.2017.8121918openalex-snapshot
A mechanistic model of memory level parallelism fed with cache miss rates
inferred← citeshttps://doi.org/10.1109/samos.2016.7818325openalex-snapshot
Concurrent memory subsystem and application optimization for ASIP design
inferred← citeshttps://doi.org/10.1145/3233182openalex-snapshot
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics
inferred← citeshttps://doi.org/10.1145/3403584openalex-snapshot
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs
inferred← citeshttps://doi.org/10.23919/date.2017.7926958openalex-snapshot
AFEC: An analytical framework for evaluating cache performance in out-of-order processors
inferred← citeshttps://doi.org/10.70675/3899fab7za569z4864zbe63z7e00f898c6b0openalex-snapshot
Modular Avionics Software Integration on Multi-Core COTS : certification-Compliant Methodology and Timing Analysis Metrics for Legacy Software Reuse in Modern Aerospace Systems
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