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Exploiting Loop-Array Dependencies to Accelerate the Design Space Exploration with High Level Synthesis
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N-PIR: A Neighborhood-Based Pareto Iterative Refinement Approach for High-Level Synthesis
inferred← citeshttps://doi.org/10.1016/j.jestch.2021.11.004openalex-snapshot
Q-PIR: A quantile based Pareto iterative refinement approach for high-level synthesis
inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.09.006openalex-snapshot
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis
inferred← citeshttps://doi.org/10.1016/j.vlsi.2023.102052openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.vlsi.2025.102513openalex-snapshot
A systematic review of machine learning-driven design space exploration in high-level synthesis
inferred← citeshttps://doi.org/10.1109/aiccsa.2017.26openalex-snapshot
Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks
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TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
inferred← citeshttps://doi.org/10.1109/dac.2018.8465940openalex-snapshot
Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
inferred← citeshttps://doi.org/10.1109/iccad.2017.8203809openalex-snapshot
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00038openalex-snapshot
Scheduling Information-Guided Efficient High-Level Synthesis Design Space Exploration
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401684openalex-snapshot
Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation
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On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
inferred← citeshttps://doi.org/10.1109/sbesc65055.2024.10771920openalex-snapshot
An Automatic Framework for Collaborative CPU Thread Throttling and FPGA HLS-Versioning
inferred← citeshttps://doi.org/10.1109/tcad.2019.2912916openalex-snapshot
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA
inferred← citeshttps://doi.org/10.1109/tcad.2019.2943570openalex-snapshot
High-Level Synthesis Design Space Exploration: Past, Present, and Future
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012750openalex-snapshot
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2023.3258341openalex-snapshot
Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue
inferred← citeshttps://doi.org/10.1145/3041219openalex-snapshot
Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies
inferred← citeshttps://doi.org/10.1145/3572959openalex-snapshot
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116309openalex-snapshot
Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization
inferred← citeshttps://doi.org/10.70675/d7388d6czb24fz476az802az93b81127a017openalex-snapshot
Parallel reconfigurable hardware architectures for video processing applications
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