On the public citation graph
PhaseNoC: TDM Scheduling at the Virtual-Channel Level for Efficient Network Traffic Isolation
0 signed · 24 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.vlsi.2017.12.003openalex-snapshot
Selective congestion control for mixed-critical networks-on-chip
inferred← citeshttps://doi.org/10.1109/access.2020.3033853openalex-snapshot
HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory
inferred← citeshttps://doi.org/10.1109/aspdac.2017.7858411openalex-snapshot
Adaptive load distribution in mixed-critical Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/dcis201949030.2019.8959943openalex-snapshot
An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00074openalex-snapshot
Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.87openalex-snapshot
ARTNoCs: An Evaluation Framework for Hardware Architectures of Real-Time NoCs
inferred← citeshttps://doi.org/10.1109/mcsoc.2019.00029openalex-snapshot
A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems
inferred← citeshttps://doi.org/10.1109/nocs.2016.7579321openalex-snapshot
Safe and dynamic traffic rate control for networks-on-chips
inferred← citeshttps://doi.org/10.1109/rtas.2017.31openalex-snapshot
Efficient Latency Guarantees for Mixed-Criticality Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/rtss.2015.37openalex-snapshot
Dynamic Control for Mixed-Critical Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/rtss.2018.00043openalex-snapshot
NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores
inferred← citeshttps://doi.org/10.1109/socc.2017.8226064openalex-snapshot
Providing throughput guarantees in mixed-criticality networks-on-chip
inferred← citeshttps://doi.org/10.1109/tc.2016.2519916openalex-snapshot
ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing
inferred← citeshttps://doi.org/10.1109/tc.2020.2987797openalex-snapshot
Enforcing Predictability of Many-Cores With DCFNoC
inferred← citeshttps://doi.org/10.1109/tcad.2018.2857298openalex-snapshot
EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems
inferred← citeshttps://doi.org/10.1109/tpds.2016.2623619openalex-snapshot
Survey on Real-Time Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2556007openalex-snapshot
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip
inferred← citeshttps://doi.org/10.1145/3412841.3441895openalex-snapshot
Partial order based non-preemptive communication scheduling towards real-time networks-on-chip
inferred← citeshttps://doi.org/10.1145/3507699openalex-snapshot
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators
inferred← citeshttps://doi.org/10.4995/thesis/10251/107336openalex-snapshot
Improving Network-on-Chip Performance in Multi-Core Systems
inferred← citeshttps://doi.org/10.4995/thesis/10251/177347openalex-snapshot
Conflict-Free Networks on Chip for Real Time Systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-114436openalex-snapshot
Probabilistically time-analyzable complex processor designs
inferred← citeshttps://doi.org/10.5821/dissertation-2117-118782openalex-snapshot
A time-predictable many-core processor design for critical real-time embedded systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-398693openalex-snapshot
Practical strategies to monitor and control contention in shared resources of critical real-time embedded systems
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.