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Dynamic Control for Mixed-Critical Networks-on-Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot
QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1049/ip-cdt:20045088openalex-snapshot
System level performance analysis – the SymTA/S approach
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/5.469298openalex-snapshot
Service disciplines for guaranteed performance service in packet-switching networks
inferredcites →https://doi.org/10.1109/date.2005.36openalex-snapshot
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip
inferredcites →https://doi.org/10.1109/iscas.2000.858698openalex-snapshot
Real-time calculus for scheduling hard real-time systems
inferredcites →https://doi.org/10.1109/nocs.2007.8openalex-snapshot
Access Regulation to Hot-Modules in Wormhole NoCs
inferredcites →https://doi.org/10.1109/nocs.2008.4492735openalex-snapshot
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
inferredcites →https://doi.org/10.1109/rtas.2010.24openalex-snapshot
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
inferredcites →https://doi.org/10.1109/rtas.2011.33openalex-snapshot
A Predictable Execution Model for COTS-Based Embedded Systems
inferredcites →https://doi.org/10.1109/rtss.2013.44openalex-snapshot
Worst Case Analysis of DRAM Latency in Multi-requestor Systems
inferredcites →https://doi.org/10.1109/rtss.2014.13openalex-snapshot
A Wormhole NoC Protocol for Mixed Criticality Systems
inferredcites →https://doi.org/10.1109/samos.2012.6404157openalex-snapshot
HNOCS: Modular open-source simulator for Heterogeneous NoCs
inferredcites →https://doi.org/10.1109/sies.2014.6871197openalex-snapshot
Supervised sharing of virtual channels in Networks -on-Chip
inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
inferredcites →https://doi.org/10.1145/1450135.1450177openalex-snapshot
Providing accurate event models for the analysis of heterogeneous multiprocessor systems
inferredcites →https://doi.org/10.1145/1629335.1629367openalex-snapshot
Handling mixed-criticality in SoC-based real-time embedded systems
inferredcites →https://doi.org/10.1145/1837274.1837353openalex-snapshot
The aethereal network on chip after ten years
inferredcites →https://doi.org/10.2197/ipsjjip.17.242openalex-snapshot
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
inferredcites →https://doi.org/10.24355/dbbs.084-200511080100-362openalex-snapshot
Compositional Scheduling Analysis Using Standard Event Models: the SymTA/S approach
inferredcites →https://doi.org/10.5555/2755753.2755874openalex-snapshot
Worst-case communication time analysis of networks-on-chip with shared virtual channels
inferredcites →https://doi.org/10.5555/2755753.2757066openalex-snapshot
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation
inferredcites →https://doi.org/10.7873/date.2015.0023openalex-snapshot
Worst-Case Communication Time Analysis of Networks-on-Chip with Shared Virtual Channels
inferredcites →https://doi.org/10.7873/date.2015.0418openalex-snapshot
PhaseNoC: TDM Scheduling at the Virtual-Channel Level for Efficient Network Traffic Isolation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-18656-2_3openalex-snapshot
A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.10.015openalex-snapshot
Ensuring safety and efficiency in networks-on-chip
inferred← citeshttps://doi.org/10.1109/ccece.2019.8861540openalex-snapshot
A Low-Latency Reconfigurable Multistage Interconnection Network
inferred← citeshttps://doi.org/10.1109/jiot.2019.2915921openalex-snapshot
MC-SDN: Supporting Mixed-Criticality Real-Time Communication Using Software-Defined Networking
inferred← citeshttps://doi.org/10.1109/jproc.2018.2858023openalex-snapshot
Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS
inferred← citeshttps://doi.org/10.1109/mc.2018.3620974openalex-snapshot
Automated Driving: The Cyber-Physical Perspective
inferred← citeshttps://doi.org/10.1109/mdat.2016.2594790openalex-snapshot
Mixed Criticality Systems—A History of Misconceptions?
inferred← citeshttps://doi.org/10.1109/nocs.2016.7579321openalex-snapshot
Safe and dynamic traffic rate control for networks-on-chips
inferred← citeshttps://doi.org/10.1109/rtcsa.2018.00024openalex-snapshot
Supporting Dynamic Voltage and Frequency Scaling in Networks-On-Chip for Hard Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtss.2018.00050openalex-snapshot
Exploiting Locality for the Performance Analysis of Shared Memory Systems in MPSoCs
inferred← citeshttps://doi.org/10.1109/rtss46320.2019.00012openalex-snapshot
Integrated Energy Control for Hard Real-Time Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tc.2016.2595581openalex-snapshot
A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems
inferred← citeshttps://doi.org/10.1109/tcad.2017.2697955openalex-snapshot
Multicore Mixed-Criticality Systems: Partitioned Scheduling and Utilization Bound
inferred← citeshttps://doi.org/10.1109/tifs.2020.2977534openalex-snapshot
Resilient System-on-Chip Designs With NoC Fabrics
inferred← citeshttps://doi.org/10.1109/tpds.2017.2677442openalex-snapshot
Resource Sharing in Multicore Mixed-Criticality Systems: Utilization Bound and Blocking Overhead
inferred← citeshttps://doi.org/10.1145/2993452.2993563openalex-snapshot
Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network
inferred← citeshttps://doi.org/10.1145/2997465.2997466openalex-snapshot
Supporting Suspension-based Locking Mechanisms for Real-Time Networks-on-chip
inferred← citeshttps://doi.org/10.1145/3131347openalex-snapshot
A Survey of Research into Mixed Criticality Systems
inferred← citeshttps://doi.org/10.1145/3528411openalex-snapshot
Application-centric Network Management - Addressing Safety and Real-time in V2X Applications
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