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Dynamic Power and Performance Back-Annotation for Fast and Accurate Functional Hardware Simulation

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Virtual Prototyping of Embedded Systems: Speed and Accuracy Tradeoffs
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A systematic review of machine learning-driven design space exploration in high-level synthesis
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High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs
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ATAPP: Architecture and Technology Aware Power Predictor for Unseen FPGAS
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Learning-based power modeling of system-level black-box IPs
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CAPEDL: Cycle-Accurate Power Estimation with Deep Learning
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SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level
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An Accurate and Quick ANN-Based System-Level Dynamic Power Estimation Model Using LLVM IR Profiling for FPGA Designs
inferred← citeshttps://doi.org/10.1145/3177865openalex-snapshot
Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs
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Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis
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Special Session: Machine Learning for Embedded System Design
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System-Level Leakage Power Estimation Model for ASIC Designs
inferred← citeshttps://doi.org/10.15598/aeee.v20i1.4229openalex-snapshot
Early Area and Power Estimation Model for Rapid System Level Design and Design Space Exploration
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DeepPM: Transformer-based Power and Performance Prediction for Energy-Aware Software
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PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
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