On the public citation graph

Exploiting short-lived variables in superscalar processors

https://doi.org/10.82308/28612
0 signed · 45 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-57502-2_61openalex-snapshot
Designing the McCAT compiler based on a family of structured intermediate representations
inferredcites →https://doi.org/10.1016/0096-0551(81)90048-5openalex-snapshot
Register allocation via coloring
inferredcites →https://doi.org/10.1109/12.4607openalex-snapshot
Implementing precise interrupts in pipelined processors
inferredcites →https://doi.org/10.1109/isca.1988.5208openalex-snapshot
The performance potential of multiple functional unit processors
inferredcites →https://doi.org/10.1109/micro.1992.697033openalex-snapshot
Partitioned Register Files For VLIWs: A Preliminary Analysis Of Tradeoffs
inferredcites →https://doi.org/10.1145/139669.140497openalex-snapshot
Data path issues in a highly concurrent machine (abstract)
inferredcites →https://doi.org/10.1145/192724.192751openalex-snapshot
Register file port requirements of transport triggered architectures
inferredcites →https://doi.org/10.1145/30350.30353openalex-snapshot
Checkpoint repair for out-of-order execution machines
inferredcites →https://doi.org/10.1145/30350.30383openalex-snapshot
WISQ: a restartable architecture using queues
inferredcites →https://doi.org/10.1145/356654.356657openalex-snapshot
Look-Ahead Processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11859802_37openalex-snapshot
Live Range Aware Cache Architecture
inferred← citeshttps://doi.org/10.1007/978-3-540-71270-1_3openalex-snapshot
LIRAC: Using Live Range Information to Optimize Memory Access
inferred← citeshttps://doi.org/10.1007/s10617-022-09264-2openalex-snapshot
Selective register-file cache: an energy saving technique for embedded processor architecture
inferred← citeshttps://doi.org/10.1007/s11227-011-0633-1openalex-snapshot
Power-aware register assignment for large register file design
inferred← citeshttps://doi.org/10.1007/s11265-014-0924-xopenalex-snapshot
Code Density and Energy Efficiency of Exposed Datapath Architectures
inferred← citeshttps://doi.org/10.1007/s11390-021-0852-8openalex-snapshot
Partial-TMR: A New Method for Protecting Register Files Against Soft Error Based on Lifetime Analysis
inferred← citeshttps://doi.org/10.1016/j.micpro.2007.10.004openalex-snapshot
Asymmetrically banked value-aware register files for low-energy and high-performance
inferred← citeshttps://doi.org/10.1016/j.sysarc.2011.02.004openalex-snapshot
Saving register-file static power by monitoring instruction sequence in ROB
inferred← citeshttps://doi.org/10.1109/71.798316openalex-snapshot
Software-directed register deallocation for simultaneous multithreaded processors
inferred← citeshttps://doi.org/10.1109/apcsac.2008.4625469openalex-snapshot
Saving register-file static power by monitoring short-lived temporary-values in ROB
inferred← citeshttps://doi.org/10.1109/dsd.2012.79openalex-snapshot
Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators
inferred← citeshttps://doi.org/10.1109/dsn.2007.99openalex-snapshot
Using Register Lifetime Predictions to Protect Register Files against Soft Errors
inferred← citeshttps://doi.org/10.1109/iccd.1998.727106openalex-snapshot
Code coalescing unit: a mechanism to facilitate load store data communication
inferred← citeshttps://doi.org/10.1109/iccd.2004.1347965openalex-snapshot
Increasing processor performance through early register release
inferred← citeshttps://doi.org/10.1109/icpp.2002.1040854openalex-snapshot
Hardware schemes for early register release
inferred← citeshttps://doi.org/10.1109/icpp.2006.20openalex-snapshot
Address-Value Decoupling for Early Register Deallocation
inferred← citeshttps://doi.org/10.1109/isca.2004.1310783openalex-snapshot
Use-based register caching with decoupled indexing
inferred← citeshttps://doi.org/10.1109/isca.2004.1310785openalex-snapshot
Physical register inlining
inferred← citeshttps://doi.org/10.1109/ispass.2000.842285openalex-snapshot
Issues in the design of store buffers in dynamically scheduled processors
inferred← citeshttps://doi.org/10.1109/isvlsi.2007.27openalex-snapshot
Asymmetrically Banked Value-Aware Register Files
inferred← citeshttps://doi.org/10.1109/lpe.2003.1231868openalex-snapshot
Reducing reorder buffer complexity through selective operand caching
inferred← citeshttps://doi.org/10.1109/lpe.2006.4271804openalex-snapshot
Selective Writeback: Exploiting Transient Values for Energy-Efficiency and Performance
inferred← citeshttps://doi.org/10.1109/lpe.2006.4271844openalex-snapshot
Register File Caching for Energy Efficiency
inferred← citeshttps://doi.org/10.1109/micro.2002.1176234openalex-snapshot
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
inferred← citeshttps://doi.org/10.1109/pact.2003.1238021openalex-snapshot
Reducing datapath energy through the isolation of short-lived operands
inferred← citeshttps://doi.org/10.1109/samos.2011.6045474openalex-snapshot
MOVE-Pro: A low power and high code density TTA architecture
inferred← citeshttps://doi.org/10.1109/tc.2004.11openalex-snapshot
Isolating short-lived operands for energy reduction
inferred← citeshttps://doi.org/10.1109/tc.2004.5openalex-snapshot
Complexity-effective reorder buffer designs for superscalar processors
inferred← citeshttps://doi.org/10.1109/tc.2006.145openalex-snapshot
Early Register Deallocation Mechanisms Using Checkpointed Register Files
inferred← citeshttps://doi.org/10.1109/tc.2007.70785openalex-snapshot
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1109/tc.2015.2395436openalex-snapshot
Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts
inferred← citeshttps://doi.org/10.1109/tvlsi.2002.801617openalex-snapshot
Low-power data forwarding for VLIW embedded architectures
inferred← citeshttps://doi.org/10.1109/tvlsi.2003.814321openalex-snapshot
Energy-efficient issue queue design
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2000243openalex-snapshot
Selective Writeback: Reducing Register File Pressure and Energy Consumption
inferred← citeshttps://doi.org/10.1145/2830772.2830784openalex-snapshot
GPU register file virtualization
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.