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Optimal software pipelining with function unit and register constraints

https://doi.org/10.82308/34918
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inferred← citeshttps://doi.org/10.1006/jpdc.1998.1442openalex-snapshot
A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards
inferred← citeshttps://doi.org/10.1007/3-540-63371-5_14openalex-snapshot
An integer linear programming model of software pipelining for the MIPS R8000 processor
inferred← citeshttps://doi.org/10.1007/978-3-540-49051-7_11openalex-snapshot
Efficient State-Diagram Construction Methods for Software Pipelining
inferred← citeshttps://doi.org/10.1007/bfb0014189openalex-snapshot
An experimental study of an ILP-based exact solution method for software pipelining
inferred← citeshttps://doi.org/10.1007/bfb0017256openalex-snapshot
Parametric computation of margins and of minimum cumulative register lifetime dates
inferred← citeshttps://doi.org/10.1007/bfb0024784openalex-snapshot
Optimal software pipelining through enumeration of schedules
inferred← citeshttps://doi.org/10.1007/bfb0026433openalex-snapshot
A new fast algorithm for optimal register allocation in modulo scheduled loops
inferred← citeshttps://doi.org/10.1007/s10766-005-6466-xopenalex-snapshot
Register Saturation in Instruction Level Parallelism
inferred← citeshttps://doi.org/10.1016/s0167-8191(99)00086-1openalex-snapshot
Compilation techniques for parallel systems
inferred← citeshttps://doi.org/10.1023/a:1018742213548openalex-snapshot
Optimal Modulo Scheduling Through Enumeration
inferred← citeshttps://doi.org/10.1109/71.544355openalex-snapshot
A framework for resource-constrained rate-optimal software pipelining
inferred← citeshttps://doi.org/10.1109/pact.1997.644005openalex-snapshot
A register pressure sensitive instruction scheduler for dynamic issue processors
inferred← citeshttps://doi.org/10.1109/tc.2003.1159750openalex-snapshot
Minimum register instruction sequencing to reduce register spills in out-of-order issue superscalar architectures
inferred← citeshttps://doi.org/10.1109/tc.2007.70752openalex-snapshot
On Periodic Register Need in Software Pipelining
inferred← citeshttps://doi.org/10.1145/207110.207128openalex-snapshot
Scheduling and mapping
inferred← citeshttps://doi.org/10.1145/231379.231385openalex-snapshot
Software pipelining showdown
inferred← citeshttps://doi.org/10.1145/371636.371709openalex-snapshot
Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems
inferred← citeshttps://doi.org/10.46586/tches.v2024.i1.87-132openalex-snapshot
Fast and Clean: Auditable high-performance assembly via constraint solving
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