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Parametric computation of margins and of minimum cumulative register lifetime dates

https://doi.org/10.1007/bfb0017256
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/net.3230080405openalex-snapshot
Primal simplex network codes: State‐of‐the‐art implementation technology
inferredcites →https://doi.org/10.1002/net.3230210105openalex-snapshot
Shortest path algorithms using dynamic breadth‐first search
inferredcites →https://doi.org/10.1002/net.3230210206openalex-snapshot
Faster parametric shortest path and minimum‐balance algorithms
inferredcites →https://doi.org/10.1007/3-540-63371-5_20openalex-snapshot
A unified software pipeline construction scheme for modulo scheduled loops
inferredcites →https://doi.org/10.1007/bf01205184openalex-snapshot
Compiling for the Cydra
inferredcites →https://doi.org/10.1007/bfb0014190openalex-snapshot
Insertion scheduling: An alternative to list scheduling for modulo schedulers
inferredcites →https://doi.org/10.1007/bfb0032706openalex-snapshot
A unified software pipeline construction scheme for modulo scheduled loops
inferredcites →https://doi.org/10.1016/0166-218x(81)90026-3openalex-snapshot
Parametric shortest path algorithms with an application to cyclic staffing
inferredcites →https://doi.org/10.1109/micro.1995.476844openalex-snapshot
Hypernode reduction modulo scheduling
inferredcites →https://doi.org/10.1137/1.9781611970265openalex-snapshot
Data Structures and Network Algorithms
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/155090.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferredcites →https://doi.org/10.1145/158511.158519openalex-snapshot
A novel framework of register allocation for software pipelining
inferredcites →https://doi.org/10.1145/192724.192731openalex-snapshot
Iterative modulo scheduling
inferredcites →https://doi.org/10.1145/231379.231385openalex-snapshot
Software pipelining showdown
inferredcites →https://doi.org/10.1145/362814.362819openalex-snapshot
An efficient search algorithm to find the elementary circuits of a graph
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/989393.989420openalex-snapshot
Software pipelining
inferredcites →https://doi.org/10.21236/ada594171openalex-snapshot
Network Flows
inferredcites →https://doi.org/10.5555/225160.225211openalex-snapshot
Hypernode reduction modulo scheduling
inferredcites →https://doi.org/10.82308/34918openalex-snapshot
Optimal software pipelining with function unit and register constraints

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9780470611227.biblioopenalex-snapshot
Bibliography
inferred← citeshttps://doi.org/10.1002/9781118625446.biblioopenalex-snapshot
Bibliography
inferred← citeshttps://doi.org/10.1007/3-540-63371-5_20openalex-snapshot
A unified software pipeline construction scheme for modulo scheduled loops
inferred← citeshttps://doi.org/10.1007/978-3-540-49051-7_19openalex-snapshot
Extending Modulo Scheduling with Memory Reference Merging
inferred← citeshttps://doi.org/10.1007/978-3-540-85097-7_41openalex-snapshot
Efficient Method for Periodic Task Scheduling with Storage Requirement Minimization
inferred← citeshttps://doi.org/10.1007/bfb0032706openalex-snapshot
A unified software pipeline construction scheme for modulo scheduled loops
inferred← citeshttps://doi.org/10.1007/s10878-010-9332-8openalex-snapshot
SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling
inferred← citeshttps://doi.org/10.1051/ro/2013036openalex-snapshot
How to eliminate non-positive circuits in periodic scheduling: a proactive strategy based on shortest path equations
inferred← citeshttps://doi.org/10.1145/2043662.2043671openalex-snapshot
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors
inferred← citeshttps://doi.org/10.1145/258915.258933openalex-snapshot
Efficient formulation for optimal modulo schedulers
inferred← citeshttps://doi.org/10.1145/258916.258933openalex-snapshot
Efficient formulation for optimal modulo schedulers
inferred← citeshttps://doi.org/10.1145/354880.354894openalex-snapshot
Code generator optimizations for the ST120 DSP-MCU core
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