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Profiling and controlling I/O‐related memory contention in COTS heterogeneous platforms

https://doi.org/10.1002/spe.3053
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Deterministic Execution Model on COTS Hardware
inferredcites →https://doi.org/10.1007/s11241-015-9229-9openalex-snapshot
A framework for memory contention analysis in multi-core platforms
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Work-conserving dynamic time-division multiplexing for multi-criticality systems
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A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems
inferredcites →https://doi.org/10.1007/s11241-020-09351-2openalex-snapshot
Supporting I/O and IPC via fine-grained OS isolation for mixed-criticality real-time tasks
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A calculus for network delay. I. Network elements in isolation
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Latency-rate servers: a general model for analysis of traffic scheduling algorithms
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Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses
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Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks
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AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC
inferredcites →https://doi.org/10.1109/dac18072.2020.9218686openalex-snapshot
Timing-Accurate General-Purpose I/O for Multi- and Many-Core Systems: Scheduling and Hardware Support
inferredcites →https://doi.org/10.1109/dac18074.2021.9586200openalex-snapshot
Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET Paradigm
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Flow regulation for on-chip communication
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Architectures and modeling of predictable memory controllers for improved system integration
inferredcites →https://doi.org/10.1109/ecrts.2015.23openalex-snapshot
WCET(m) Estimation in Multi-core Systems Using Single Core Equivalence
inferredcites →https://doi.org/10.1109/ecrts.2015.24openalex-snapshot
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems
inferredcites →https://doi.org/10.1109/ecrts.2016.14openalex-snapshot
Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform
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Supporting temporal and spatial isolation in a hypervisor for ARM multicore platforms
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SD-VBS: The San Diego Vision Benchmark Suite
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An Analyzable Memory Controller for Hard Real-Time CMPs
inferredcites →https://doi.org/10.1109/rtas.2011.33openalex-snapshot
A Predictable Execution Model for COTS-Based Embedded Systems
inferredcites →https://doi.org/10.1109/rtas.2014.6925998openalex-snapshot
Bounding memory interference delay in COTS-based multi-core systems
inferredcites →https://doi.org/10.1109/rtas.2014.6925999openalex-snapshot
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms
inferredcites →https://doi.org/10.1109/rtas.2016.7461321openalex-snapshot
A Real-Time Scratchpad-Centric OS for Multi-Core Embedded Systems
inferredcites →https://doi.org/10.1109/rtas.2016.7461361openalex-snapshot
Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems
inferredcites →https://doi.org/10.1109/rtas.2018.00013openalex-snapshot
BlueVisor: A Scalable Real-Time Hardware Hypervisor for Many-Core Embedded Systems
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Achieving Predictable Multicore Execution of Automotive Applications Using the LET Paradigm
inferredcites →https://doi.org/10.1109/rtas.2019.00009openalex-snapshot
Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems
inferredcites →https://doi.org/10.1109/rtas48715.2020.00-15openalex-snapshot
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
inferredcites →https://doi.org/10.1109/rtas48715.2020.000-3openalex-snapshot
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling
inferredcites →https://doi.org/10.1109/rtas48715.2020.00011openalex-snapshot
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors
inferredcites →https://doi.org/10.1109/rtas52030.2021.00032openalex-snapshot
Latency Analysis of I/O Virtualization Techniques in Hypervisor-Based Real-Time Systems
inferredcites →https://doi.org/10.1109/rtcsa.2019.8864563openalex-snapshot
Memory Bandwidth Regulation for Multiframe Task Sets
inferredcites →https://doi.org/10.1109/rtss.2007.15openalex-snapshot
Toward the Predictable Integration of Real-Time COTS Based Systems
inferredcites →https://doi.org/10.1109/rtss.2007.51openalex-snapshot
Static Scheduling and Software Synthesis for Dataflow Graphs with Symbolic Model-Checking
inferredcites →https://doi.org/10.1109/rtss.2008.42openalex-snapshot
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
inferredcites →https://doi.org/10.1109/rtss.2009.41openalex-snapshot
Real-Time Control of I/O COTS Peripherals for Embedded Systems
inferredcites →https://doi.org/10.1109/rtss.2016.035openalex-snapshot
BUNDLE: Real-Time Multi-threaded Scheduling to Reduce Cache Contention
inferredcites →https://doi.org/10.1109/rtss.2018.00040openalex-snapshot
Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems
inferredcites →https://doi.org/10.1109/rtss49844.2020.00039openalex-snapshot
E-WarP: A System-wide Framework for Memory Bandwidth Profiling and Management
inferredcites →https://doi.org/10.1109/sies.2014.6871199openalex-snapshot
Dynamic budgeting for settling DRAM contention of co-running hard and soft real-time tasks
inferredcites →https://doi.org/10.1109/tc.2009.156openalex-snapshot
Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems
inferredcites →https://doi.org/10.1109/tc.2011.202openalex-snapshot
Real-Time I/O Management System with COTS Peripherals
inferredcites →https://doi.org/10.1109/tc.2020.2974224openalex-snapshot
Schedulability Analysis of Global Scheduling for Multicore Systems With Shared Caches
inferredcites →https://doi.org/10.1109/tcad.2018.2857379openalex-snapshot
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems
inferredcites →https://doi.org/10.1109/tcad.2020.3012210openalex-snapshot
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms
inferredcites →https://doi.org/10.1145/1289816.1289877openalex-snapshot
Predator
inferredcites →https://doi.org/10.1145/2516821.2516826openalex-snapshot
Quality of service capabilities for hard real-time applications on multi-core processors
inferredcites →https://doi.org/10.1145/2830555openalex-snapshot
A Survey on Cache Management Mechanisms for Real-Time Embedded Systems
inferredcites →https://doi.org/10.1145/3126496openalex-snapshot
Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures
inferredcites →https://doi.org/10.1145/3126556openalex-snapshot
Edge-TM
inferredcites →https://doi.org/10.1145/3139258.3139270openalex-snapshot
SiGAMMA
inferredcites →https://doi.org/10.1145/3273905.3273911openalex-snapshot
Supporting I/O and IPC via Fine-Grained OS Isolation for Mixed-Criticality Real-Time Tasks
inferredcites →https://doi.org/10.1145/3309765openalex-snapshot
BlueIO
inferredcites →https://doi.org/10.1145/3323212openalex-snapshot
A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems
inferredcites →https://doi.org/10.1145/3358192openalex-snapshot
Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference
inferredcites →https://doi.org/10.23919/date.2017.7927099openalex-snapshot
GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systems
inferredcites →https://doi.org/10.23919/date.2018.8342211openalex-snapshot
Mixed-criticality scheduling with memory bandwidth regulation
inferredcites →https://doi.org/10.4230/lipics.ecrts.2017.3openalex-snapshot
WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment
inferredcites →https://doi.org/10.4230/lipics.ecrts.2019.25openalex-snapshot
Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Synchronous VS asynchronous reconfiguration of Memory Bandwidth Management Schemes: A comparative analysis
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Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1109/dsn-s65789.2025.00044openalex-snapshot
Observe and Regulate Memory Interference on MPSoC: a Practical Approach
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Denial-of-Service Attacks on Shared Resources in Intel’s Integrated CPU-GPU Platforms
inferred← citeshttps://doi.org/10.1109/isorc70347.2026.11605627openalex-snapshot
DRAM Bank-Aware Memory Allocation for Embedded Real-Time Virtualization
inferred← citeshttps://doi.org/10.1109/rtas58335.2023.00011openalex-snapshot
Shedding Light on Static Partitioning Hypervisors for Arm-based Mixed-Criticality Systems
inferred← citeshttps://doi.org/10.1109/rtas58335.2023.00026openalex-snapshot
MemPol: Policing Core Memory Bandwidth from Outside of the Cores
inferred← citeshttps://doi.org/10.1109/rtas61025.2024.00020openalex-snapshot
DAG Scheduling with Execution Groups
inferred← citeshttps://doi.org/10.1109/rtas68450.2026.00026openalex-snapshot
ETM 2 : Empowering Traditional Memory Bandwidth Regulation using ETM
inferred← citeshttps://doi.org/10.1109/rtas68450.2026.00027openalex-snapshot
ROSBand: A Bandwidth Regulation Approach on ROS2-Based Systems
inferred← citeshttps://doi.org/10.1109/rtcsa58653.2023.00014openalex-snapshot
BandWatch: A System-Wide Memory Bandwidth Regulation System for Heterogeneous Multicore
inferred← citeshttps://doi.org/10.1109/rtcsa58653.2023.00015openalex-snapshot
IRQ Coloring and the Subtle Art of Mitigating Interrupt-Generated Interference
inferred← citeshttps://doi.org/10.1109/rtcsa66114.2025.00022openalex-snapshot
Predictable Memory Bandwidth Regulation for DynamIQ Arm Systems
inferred← citeshttps://doi.org/10.1109/rtcsa66114.2025.00027openalex-snapshot
Beyond the Bermuda Triangle of Contention: IOMMU Interference in Mixed Criticality Systems
inferred← citeshttps://doi.org/10.1109/rtcsa71153.2026.00018openalex-snapshot
Contention Behind the Wheel: Characterizing and Mitigating Interference in Next-Gen Automotive MCUs
inferred← citeshttps://doi.org/10.1109/rtcsa71153.2026.00030openalex-snapshot
LMS-AR: LMS Prediction-Based Adaptive Regulator for Memory Bandwidth in Multicore Systems
inferred← citeshttps://doi.org/10.1109/rtss55097.2022.00038openalex-snapshot
CAESAR: Coherence-Aided Elective and Seamless Alternative Routing via on-chip FPGA
inferred← citeshttps://doi.org/10.1109/rtss62706.2024.00035openalex-snapshot
Coherence-Aided Memory Bandwidth Regulation
inferred← citeshttps://doi.org/10.1109/tc.2022.3202720openalex-snapshot
Analyzing Arm's MPAM From the Perspective of Time Predictability
inferred← citeshttps://doi.org/10.1109/tcad.2022.3202434openalex-snapshot
An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/tcad.2024.3449237openalex-snapshot
Learning Memory-Contention Timing Models With Automated Platform Profiling
inferred← citeshttps://doi.org/10.1109/tpds.2024.3513416openalex-snapshot
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-Based Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1145/3765736openalex-snapshot
Virtualization Technology for Dependable Embedded Systems: A Survey for Transportation and Industrial Domains
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HOME: A Hierarchy-Oriented Memory Evaluation Framework for Fast Contention Analysis
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