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Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference

https://doi.org/10.1145/3358192
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1038/s41928-018-0059-3openalex-snapshot
Scaling for edge inference of deep neural networks
inferredcites →https://doi.org/10.1109/cvpr.1993openalex-snapshot
Proceedings of IEEE Conference on Computer Vision and Pattern Recognition
inferredcites →https://doi.org/10.1109/cvpr.2016.91openalex-snapshot
You Only Look Once: Unified, Real-Time Object Detection
inferredcites →https://doi.org/10.1109/cvpr.2018.00866openalex-snapshot
Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation
inferredcites →https://doi.org/10.1109/fccm.2016.22openalex-snapshot
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1109/fccm.2018.00021openalex-snapshot
FPDeep: Acceleration and Load Balancing of CNN Training on FPGA Clusters
inferredcites →https://doi.org/10.1109/hotchips.2014.7478821openalex-snapshot
SDA: Software-defined accelerator for large-scale DNN systems
inferredcites →https://doi.org/10.1109/isca.2018.00012openalex-snapshot
A Configurable Cloud-Scale DNN Processor for Real-Time AI
inferredcites →https://doi.org/10.1109/isqed.2018.8357326openalex-snapshot
Resource constrained cellular neural networks for real-time obstacle detection using FPGAs
inferredcites →https://doi.org/10.1109/isvlsi.2016.129openalex-snapshot
Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware
inferredcites →https://doi.org/10.1109/les.2018.2815954openalex-snapshot
Cappuccino: Efficient CNN Inference Software Synthesis for Mobile System-on-Chips
inferredcites →https://doi.org/10.1109/mci.2018.2840738openalex-snapshot
Recent Trends in Deep Learning Based Natural Language Processing [Review Article]
inferredcites →https://doi.org/10.1109/mm.2018.022071131openalex-snapshot
Serving DNNs in Real Time at Datacenter Scale with Project Brainwave
inferredcites →https://doi.org/10.1109/tc.2018.2864749openalex-snapshot
Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router
inferredcites →https://doi.org/10.1109/tcad.2018.2857098openalex-snapshot
Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNs
inferredcites →https://doi.org/10.1109/tcad.2018.2873210openalex-snapshot
OPTiC: Optimizing Collaborative CPU–GPU Computing on Mobile Devices With Thermal Constraints
inferredcites →https://doi.org/10.1109/tcad.2020.2986127openalex-snapshot
Hardware/Software Co-Exploration of Neural Architectures
inferredcites →https://doi.org/10.1109/tpami.2016.2577031openalex-snapshot
Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks
inferredcites →https://doi.org/10.1109/tpds.2016.2643669openalex-snapshot
FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era
inferredcites →https://doi.org/10.1109/tpds.2018.2791440openalex-snapshot
Towards Memory-Efficient Allocation of CNNs on Processing-in-Memory Architecture
inferredcites →https://doi.org/10.1109/tpds.2018.2868062openalex-snapshot
Exploiting Parallelism for CNN Applications on 3D Stacked Processing-In-Memory Architecture
inferredcites →https://doi.org/10.1145/1347375.1347389openalex-snapshot
The worst-case execution-time problem—overview of methods and survey of tools
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2847263.2847276openalex-snapshot
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2934583.2934644openalex-snapshot
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
inferredcites →https://doi.org/10.1145/3020078.3021736openalex-snapshot
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3061639.3062323openalex-snapshot
Task Mapping on SMART NoC
inferredcites →https://doi.org/10.1145/3065386openalex-snapshot
ImageNet classification with deep convolutional neural networks
inferredcites →https://doi.org/10.1145/3079856.3080221openalex-snapshot
Maximizing CNN Accelerator Efficiency Through Resource Partitioning
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3140659.3080221openalex-snapshot
Maximizing CNN Accelerator Efficiency Through Resource Partitioning
inferredcites →https://doi.org/10.1145/3140659.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3240765.3240801openalex-snapshot
DNNBuilder
inferredcites →https://doi.org/10.1145/3289602.3293935openalex-snapshot
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System
inferredcites →https://doi.org/10.1145/3316781.3317757openalex-snapshot
Accuracy vs. Efficiency
inferredcites →https://doi.org/10.1145/3316781.3317906openalex-snapshot
Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System
inferredcites →https://doi.org/10.23919/date.2019.8715021openalex-snapshot
Towards Cross-Platform Inference on Edge Devices with Emerging Neuromorphic Architecture
inferredcites →https://doi.org/10.23919/date.2019.8715174openalex-snapshot
An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures
inferredcites →https://doi.org/10.48550/arxiv.1708.02709openalex-snapshot
Recent Trends in Deep Learning Based Natural Language Processing
inferredcites →https://doi.org/10.48550/arxiv.1802.03646openalex-snapshot
On the Universal Approximability and Complexity Bounds of Quantized ReLU Neural Networks
inferredcites →https://doi.org/10.48550/arxiv.1901.11211openalex-snapshot
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Field programmable gate array‐based all‐layer accelerator with quantization neural networks for sustainable cyber‐physical systems
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Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA
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Hardware–Software Co-design of Deep Neural Architectures: From FPGAs and ASICs to Computing-in-Memories
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Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems
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Breast cancer classification using deep learning and FPGA inferencing
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When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies
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Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence
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Automating Deep Neural Network Model Selection for Edge Inference
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3D CNN Acceleration on FPGA using Hardware-Aware Pruning
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Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices
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Distributed Recommendation Inference on FPGA Clusters
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FPGA Based Co-design of Storage-side Query Filter for Big Data Systems
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Conception d’une plate-forme multi-FPGAs dans le cloud pour les applications de réseaux de neurones
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