On the public citation graph
AES on FPGA from the Fastest to the Smallest
0 signed · 209 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44709-1_7openalex-snapshot
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
inferredcites →https://doi.org/10.1007/3-540-45682-1_15openalex-snapshot
A Compact Rijndael Hardware Architecture with S-Box Optimization
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_26openalex-snapshot
Strong Authentication for RFID Systems Using the AES Algorithm
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_58openalex-snapshot
A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_59openalex-snapshot
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_29openalex-snapshot
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_26openalex-snapshot
Very Compact FPGA Implementation of the AES Algorithm
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_27openalex-snapshot
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
inferredcites →https://doi.org/10.1109/fccm.2004.1openalex-snapshot
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
inferredcites →https://doi.org/10.1109/itcc.2004.1286716openalex-snapshot
Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
inferredcites →https://doi.org/10.1109/tvlsi.2004.832943openalex-snapshot
High-speed VLSI architectures for the AES algorithm
inferredcites →https://doi.org/10.1145/611817.611848openalex-snapshot
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781118468654.ch14openalex-snapshot
Reconfigurable Architecture for Cryptography over Binary Finite Fields
inferred← citeshttps://doi.org/10.1002/sec.1138openalex-snapshot
An efficient single unit T‐box/T−1‐box implementation for 128‐bit AES on FPGA
inferred← citeshttps://doi.org/10.1002/sec.651openalex-snapshot
FPGA implementation of AES algorithm for high throughput using folded parallel architecture
inferred← citeshttps://doi.org/10.1007/11807964_38openalex-snapshot
Energy Comparison of AES and SHA-1 for Ubiquitous Computing
inferred← citeshttps://doi.org/10.1007/11908739_24openalex-snapshot
On the Effectiveness of TMTO and Exhaustive Search Attacks
inferred← citeshttps://doi.org/10.1007/978-0-387-71817-0_10openalex-snapshot
FPGA and ASIC Implementations of AES
inferred← citeshttps://doi.org/10.1007/978-0-387-71817-0_11openalex-snapshot
Secure and Efficient Implementation of Symmetric Encryption Schemes using FPGAs
inferred← citeshttps://doi.org/10.1007/978-0-387-71817-0_12openalex-snapshot
Block Cipher Modes of Operation from a Hardware Implementation Perspective
inferred← citeshttps://doi.org/10.1007/978-1-4614-1362-2openalex-snapshot
Embedded Systems Design with FPGAs
inferred← citeshttps://doi.org/10.1007/978-1-4614-1362-2_10openalex-snapshot
Compact CLEFIA Implementation on FPGAs
inferred← citeshttps://doi.org/10.1007/978-1-4614-7915-4_9openalex-snapshot
A Survey of Recent Results in FPGA Security and Intellectual Property Protection
inferred← citeshttps://doi.org/10.1007/978-3-030-38501-9_28openalex-snapshot
Improved Crypto Algorithm for High-Speed Internet of Things (IoT) Applications
inferred← citeshttps://doi.org/10.1007/978-3-031-85363-0_33openalex-snapshot
Area Optimized Architectures for Galois Counter Mode
inferred← citeshttps://doi.org/10.1007/978-3-319-09879-1_22openalex-snapshot
Combined AES + AEGIS Architectures for High Performance and Lightweight Security Applications
inferred← citeshttps://doi.org/10.1007/978-3-319-12060-7_9openalex-snapshot
Khudra: A New Lightweight Block Cipher for FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-319-13039-2_18openalex-snapshot
A Very Compact FPGA Implementation of LED and PHOTON
inferred← citeshttps://doi.org/10.1007/978-3-319-16214-0_19openalex-snapshot
Dual CLEFIA/AES Cipher Core on FPGA
inferred← citeshttps://doi.org/10.1007/978-3-319-26617-6_18openalex-snapshot
BitCryptor: Bit-Serialized Flexible Crypto Engine for Lightweight Applications
inferred← citeshttps://doi.org/10.1007/978-3-319-44318-8_1openalex-snapshot
AES Datapaths on FPGAs: A State of the Art Analysis
inferred← citeshttps://doi.org/10.1007/978-3-319-50057-7_7openalex-snapshot
FPGA-Based IP and SoC Security
inferred← citeshttps://doi.org/10.1007/978-3-319-50380-6_9openalex-snapshot
Ultra-Lightweight Implementation in Area of Block Ciphers
inferred← citeshttps://doi.org/10.1007/978-3-540-68164-9_2openalex-snapshot
Implementation of the AES-128 on Virtex-5 FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-540-70550-5_12openalex-snapshot
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors
inferred← citeshttps://doi.org/10.1007/978-3-540-73625-7_45openalex-snapshot
Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks
inferred← citeshttps://doi.org/10.1007/978-3-540-77026-8_33openalex-snapshot
Efficient Implementations of Some Tweakable Enciphering Schemes in Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1007/978-3-540-89754-5_28openalex-snapshot
Chai-Tea, Cryptographic Hardware Implementations of xTEA
inferred← citeshttps://doi.org/10.1007/978-3-642-00641-8_20openalex-snapshot
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-642-13708-2_10openalex-snapshot
High Performance GHASH Function for Long Messages
inferred← citeshttps://doi.org/10.1007/978-3-642-37288-9_12openalex-snapshot
Putting together What Fits together - GrÆStl
inferred← citeshttps://doi.org/10.1007/978-3-662-45355-1_16openalex-snapshot
Evaluation of Format- Preserving Encryption Algorithms for Critical Infrastructure Protection
inferred← citeshttps://doi.org/10.1007/978-3-662-49297-0_4openalex-snapshot
Der Advanced Encryption Standard
inferred← citeshttps://doi.org/10.1007/978-981-10-8899-5_5openalex-snapshot
Examples of Reconfigurable Cryptographic Processor Design
inferred← citeshttps://doi.org/10.1007/978-981-16-0275-7_29openalex-snapshot
High Throughput Pipelined Architecture for AES Cipher
inferred← citeshttps://doi.org/10.1007/978-981-19-6383-4_4openalex-snapshot
A Survey on Performance Analysis of Different Architectures of AES Algorithm on FPGA
inferred← citeshttps://doi.org/10.1007/978-981-99-4634-1_28openalex-snapshot
FPGA Implementation of SLIM an Ultra-Lightweight Block Cipher for IoT Applications
inferred← citeshttps://doi.org/10.1007/s10617-017-9189-5openalex-snapshot
FPGA implementation of an optimized key expansion module of AES algorithm for secure transmission of personal ECG signals
inferred← citeshttps://doi.org/10.1007/s10845-012-0671-4openalex-snapshot
Analyzing and comparing the AES architectures for their power consumption
inferred← citeshttps://doi.org/10.1007/s11042-019-7587-3openalex-snapshot
Design and Implementation of novel datapath designs of lightweight cipher RECTANGLE for resource constrained environment
inferred← citeshttps://doi.org/10.1007/s11227-016-1929-yopenalex-snapshot
Hardware coprocessors for high-performance symmetric cryptography
inferred← citeshttps://doi.org/10.1007/s11277-016-3385-7openalex-snapshot
An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box
inferred← citeshttps://doi.org/10.1007/s13389-011-0002-2openalex-snapshot
Utilizing hard cores of modern FPGA devices for high-performance cryptography
inferred← citeshttps://doi.org/10.1007/s13389-011-0009-8openalex-snapshot
A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO
inferred← citeshttps://doi.org/10.1007/s13389-011-0013-zopenalex-snapshot
High performance GHASH and impacts of a class of unconventional bases
inferred← citeshttps://doi.org/10.1007/s13389-013-0060-8openalex-snapshot
A new power-aware FPGA design metric
inferred← citeshttps://doi.org/10.1007/s13389-025-00388-2openalex-snapshot
First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES
inferred← citeshttps://doi.org/10.1007/s44443-026-01213-4openalex-snapshot
From one to three: multi-entry persistent fault analysis of Ascon
inferred← citeshttps://doi.org/10.1016/j.jnca.2014.09.006openalex-snapshot
A comprehensive survey of modern symmetric cryptographic solutions for resource constrained environments
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.01.029openalex-snapshot
A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl
inferred← citeshttps://doi.org/10.1016/j.measurement.2010.03.002openalex-snapshot
Multi-core implementation of the symmetric cryptography algorithms in the measurement system
inferred← citeshttps://doi.org/10.1016/j.mejo.2008.11.044openalex-snapshot
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
inferred← citeshttps://doi.org/10.1016/j.mejo.2014.05.004openalex-snapshot
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
inferred← citeshttps://doi.org/10.1016/j.mejo.2020.104704openalex-snapshot
Stability Enhancing SRAM cell for low power LUT Design
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.07.005openalex-snapshot
An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.11.015openalex-snapshot
A high performance ST-Box based unified AES encryption/decryption architecture on FPGA
inferred← citeshttps://doi.org/10.1016/j.phpro.2012.05.242openalex-snapshot
A SOPC-BASED Evaluation of AES for 2.4 GHz Wireless Network
inferred← citeshttps://doi.org/10.1016/j.procs.2017.03.075openalex-snapshot
Automatic Security Analysis of EPCBC against Differential Attacks
inferred← citeshttps://doi.org/10.1016/j.protcy.2016.05.066openalex-snapshot
Design of AES Architecture With Area and Speed Tradeoff
inferred← citeshttps://doi.org/10.1016/j.vlsi.2009.05.003openalex-snapshot
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
inferred← citeshttps://doi.org/10.1049/iet-cds.2018.5354openalex-snapshot
8‐bit serialised architecture of SEED block cipher for constrained devices
inferred← citeshttps://doi.org/10.1049/iet-cdt.2014.0101openalex-snapshot
High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion
inferred← citeshttps://doi.org/10.1049/iet-ifs.2015.0401openalex-snapshot
Compact and low‐power ASIP design for lightweight PUF‐based authentication protocols
inferred← citeshttps://doi.org/10.1063/5.0103349openalex-snapshot
A review of traditional, lightweight and ultra-lightweight cryptography techniques for IoT security environment
inferred← citeshttps://doi.org/10.1080/00051144.2020.1816388openalex-snapshot
FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
inferred← citeshttps://doi.org/10.1080/09720529.2012.10698389openalex-snapshot
Performance of AES using new instruction with Intel(r) core processor
inferred← citeshttps://doi.org/10.1093/ietfec/e91-a.1.211openalex-snapshot
Diversification of Processors Based on Redundancy in Instruction Set
inferred← citeshttps://doi.org/10.1109/access.2020.3034832openalex-snapshot
A Novel Algebraic Technique for Design of Computational Substitution-Boxes Using Action of Matrices on Galois Field
inferred← citeshttps://doi.org/10.1109/access.2024.3372388openalex-snapshot
SHC: 8-bit Compact and Efficient S-Box Structure for Lightweight Cryptography
inferred← citeshttps://doi.org/10.1109/aimlcps68702.2026.11542469openalex-snapshot
High-Performance AES-128 Implementation on FPGA: A Comparative Study
inferred← citeshttps://doi.org/10.1109/asap.2016.7760769openalex-snapshot
A grain in the silicon: SCA-protected AES in less than 30 slices
inferred← citeshttps://doi.org/10.1109/asicon47005.2019.8983486openalex-snapshot
On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper
inferred← citeshttps://doi.org/10.1109/cecit53797.2021.00020openalex-snapshot
A Lightweight Secure Mutual Authentication Protocol for IoT Devices
inferred← citeshttps://doi.org/10.1109/cicc.2019.8780386openalex-snapshot
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper
inferred← citeshttps://doi.org/10.1109/cis58238.2022.00088openalex-snapshot
A 32-bit efficient subpipelined architecture for AES encryption and decryption
inferred← citeshttps://doi.org/10.1109/cise.2010.5676905openalex-snapshot
Design and Efficient FPGA Implementation of Ghash Core for AES-GCM
inferred← citeshttps://doi.org/10.1109/cit.2016.45openalex-snapshot
Efficient Hybrid Encryption System Based on Block Cipher and Chaos Generator
inferred← citeshttps://doi.org/10.1109/cnt.2014.7062766openalex-snapshot
Implementation of pipelined hardware architecture for AES algorithm using FPGA
inferred← citeshttps://doi.org/10.1109/comst.2026.3680907openalex-snapshot
Evaluating the Timeliness of Cryptography for Securing ICS Protocols in Smart Grid
inferred← citeshttps://doi.org/10.1109/conielecomp.2016.7438557openalex-snapshot
An evaluation of AES and present ciphers for lightweight cryptography on smartphones
inferred← citeshttps://doi.org/10.1109/csnt51715.2021.9509662openalex-snapshot
Energy-efficient implementation of AES algorithm on 16nm FPGA
inferred← citeshttps://doi.org/10.1109/discover55800.2022.9974925openalex-snapshot
Low power and area efficient AES implementation using ROM based key expansion and rotational shift
inferred← citeshttps://doi.org/10.1109/dsd.2006.40openalex-snapshot
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
inferred← citeshttps://doi.org/10.1109/dsd.2014.90openalex-snapshot
Parameterized AES-Based Crypto Processor for FPGAs
inferred← citeshttps://doi.org/10.1109/dsr.2011.6026856openalex-snapshot
A secure, configurable and customized multimode Bulk Encryptor
inferred← citeshttps://doi.org/10.1109/ecctd.2007.4529608openalex-snapshot
A high-speed hardware implementation of the Hermes8-128 stream cipher
inferred← citeshttps://doi.org/10.1109/eit.2009.5189651openalex-snapshot
Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology
inferred← citeshttps://doi.org/10.1109/elcon-cp69823.2026.11452168openalex-snapshot
Architecture and Power-Balancing Effects on Side-Channel Leakage Protection in AES Hardware Implementations
inferred← citeshttps://doi.org/10.1109/fpl.2007.4380694openalex-snapshot
Compact AES-Based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation
inferred← citeshttps://doi.org/10.1109/fpl.2009.5272349openalex-snapshot
Compact FPGA implementation of Camellia
inferred← citeshttps://doi.org/10.1109/fpl.2009.5272377openalex-snapshot
Synthesis of the SR programming language for complex FPGAs
inferred← citeshttps://doi.org/10.1109/fpl.2011.101openalex-snapshot
Compact CLEFIA Implementation on FPGAS
inferred← citeshttps://doi.org/10.1109/fpl.2012.6339250openalex-snapshot
Low area memory-free FPGA implementation of the AES algorithm
inferred← citeshttps://doi.org/10.1109/fpl.2015.7293948openalex-snapshot
Compact dual block AES core on FPGA for CCM Protocol
inferred← citeshttps://doi.org/10.1109/fpt.2007.4439248openalex-snapshot
Efficient and High-Throughput Implementations of AES-GCM on FPGAs
inferred← citeshttps://doi.org/10.1109/fpt.2010.5681776openalex-snapshot
Compact implementations of BLAKE-32 and BLAKE-64 on FPGA
inferred← citeshttps://doi.org/10.1109/glocom.2010.5684215openalex-snapshot
A Lightweight Stream Cipher WG-7 for RFID Encryption and Authentication
inferred← citeshttps://doi.org/10.1109/glocomw.2010.5700456openalex-snapshot
A high-speed key exchange multi-core SoC architecture for IPSec real-time Internet traffic
inferred← citeshttps://doi.org/10.1109/hpec.2017.8091062openalex-snapshot
High-performance low-energy implementation of cryptographic algorithms on a programmable SoC for IoT devices
inferred← citeshttps://doi.org/10.1109/hpec58863.2023.10363592openalex-snapshot
Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1109/hst.2010.5513116openalex-snapshot
FPGA implementations of the Hummingbird cryptographic algorithm
inferred← citeshttps://doi.org/10.1109/hst.2014.6855581openalex-snapshot
NREPO: Normal basis Recomputing with Permuted Operands
inferred← citeshttps://doi.org/10.1109/hst.2015.7140227openalex-snapshot
Silent Simon: A threshold implementation under 100 slices
inferred← citeshttps://doi.org/10.1109/iccad.2014.7001346openalex-snapshot
Cryptoraptor: High throughput reconfigurable cryptographic processor
inferred← citeshttps://doi.org/10.1109/icccn.2011.6005765openalex-snapshot
XTEA Based Secure Authentication Protocol for RFID Systems
inferred← citeshttps://doi.org/10.1109/iccsce.2015.7482148openalex-snapshot
FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture
inferred← citeshttps://doi.org/10.1109/iccsit.2009.5234770openalex-snapshot
Implementation and comparative analysis of AES as a stream cipher
inferred← citeshttps://doi.org/10.1109/icdcs.2017.86openalex-snapshot
A General Purpose Testbed for Mobile Data Gathering in Wireless Sensor Networks and a Case Study
inferred← citeshttps://doi.org/10.1109/icecs.2010.5724640openalex-snapshot
Exploration of cryptographic ASIP designs for wireless sensor nodes
inferred← citeshttps://doi.org/10.1109/icecs.2013.6815431openalex-snapshot
FPGA implementation of AES-based crypto processor
inferred← citeshttps://doi.org/10.1109/icecs.2018.8617998openalex-snapshot
A 4-bit Architecture of SEED Block Cipher for IoT Applications
inferred← citeshttps://doi.org/10.1109/icetet.2012.53openalex-snapshot
FPGA Implementation of High Speed VLSI Architectures for AES Algorithm
inferred← citeshttps://doi.org/10.1109/icoecit68303.2026.11497061openalex-snapshot
Evaluation and Future Exploration of Lightweight Cryptography on FPGA: Challenges and Opportunities for AES, TEA, and PRESENT
inferred← citeshttps://doi.org/10.1109/icoei68323.2026.11541675openalex-snapshot
Hardware Implementation of AES-256 Encryption on FPGA for Real-Time Video Stream Security
inferred← citeshttps://doi.org/10.1109/icrieece44171.2018.9009347openalex-snapshot
Security in Opportunistic Sensor Network and IoT having Sensors using Light Weight Key Generation and Cryptographic Algorithm
inferred← citeshttps://doi.org/10.1109/icsict.2010.5667347openalex-snapshot
AES implementation based on a configurable VLIW DSP
inferred← citeshttps://doi.org/10.1109/icspc.2007.4728419openalex-snapshot
High Performance AES Design using Pipelining Structure over GF((24)2)
inferred← citeshttps://doi.org/10.1109/icstcc.2016.7790658openalex-snapshot
A flexible system-on-a-chip implementation of the Advanced Encryption Standard
inferred← citeshttps://doi.org/10.1109/iisr.2018.8535613openalex-snapshot
Implementation of SM4 on FPGA: Trade-Off Analysis between Area and Speed
inferred← citeshttps://doi.org/10.1109/imsaa.2011.6156342openalex-snapshot
High speed S-box architecture for Advanced Encryption Standard
inferred← citeshttps://doi.org/10.1109/imtc.2011.5944315openalex-snapshot
Implementation of symmetric cryptography in embedded systems for secure measurement systems
inferred← citeshttps://doi.org/10.1109/iotsms48152.2019.8939241openalex-snapshot
A Fast and Efficient Datapath Designs of Lightweight Cipher RoadRunneR on FPGA’s for Resource Constrained Environments
inferred← citeshttps://doi.org/10.1109/iscas.2006.1692639openalex-snapshot
AES as stream cipher on a small FPGA
inferred← citeshttps://doi.org/10.1109/iscisc.2015.7387896openalex-snapshot
A low-cost and flexible FPGA implementation for SPECK block Cipher
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-socialcom-sustaincom52081.2021.00161openalex-snapshot
A hybrid CPU/GPU Scheme for Optimizing ChaCha20 Stream Cipher
inferred← citeshttps://doi.org/10.1109/isvlsi.2012.25openalex-snapshot
Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers
inferred← citeshttps://doi.org/10.1109/jiot.2018.2864513openalex-snapshot
FPGA-Based Symmetric Re-Encryption Scheme to Secure Data Processing for Cloud-Integrated Internet of Things
inferred← citeshttps://doi.org/10.1109/jssc.2014.2384039openalex-snapshot
340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
inferred← citeshttps://doi.org/10.1109/les.2014.2314961openalex-snapshot
SIMON Says: Break Area Records of Block Ciphers on FPGAs
inferred← citeshttps://doi.org/10.1109/milcom.2010.5680127openalex-snapshot
FPGA-based, multi-processor HW-SW system for Single-Chip Crypto applications
inferred← citeshttps://doi.org/10.1109/mue.2008.94openalex-snapshot
High-Speed Implementations of Block Cipher ARIA Using Graphics Processing Units
inferred← citeshttps://doi.org/10.1109/nca.2014.52openalex-snapshot
Hardware Implementation of Quasigroup Encryption for SCADA Networks
inferred← citeshttps://doi.org/10.1109/reconfig.2009.54openalex-snapshot
Lightweight Cryptography for FPGAs
inferred← citeshttps://doi.org/10.1109/sips.2006.352569openalex-snapshot
High-Speed Pipelined EGG Processor on FPGA
inferred← citeshttps://doi.org/10.1109/spl.2009.4914893openalex-snapshot
Design space exploration of present implementations for FPGAS
inferred← citeshttps://doi.org/10.1109/tc.2010.64openalex-snapshot
Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
inferred← citeshttps://doi.org/10.1109/tc.2011.227openalex-snapshot
Efficient hardware implementations of brw polynomials and tweakable enciphering schemes
inferred← citeshttps://doi.org/10.1109/tcad.2013.2263037openalex-snapshot
Recomputing with Permuted Operands: A Concurrent Error Detection Approach
inferred← citeshttps://doi.org/10.1109/tcad.2018.2801229openalex-snapshot
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms
inferred← citeshttps://doi.org/10.1109/tcc.2020.2992548openalex-snapshot
When FPGA Meets Cloud: A First Look at Performance
inferred← citeshttps://doi.org/10.1109/tdsc.2019.2933214openalex-snapshot
Secure Computing Enclaves Using FPGAs
inferred← citeshttps://doi.org/10.1109/telfor.2016.7818860openalex-snapshot
IP core for AES256 and TDES algorithms with AXI interface
inferred← citeshttps://doi.org/10.1109/tifs.2011.2169667openalex-snapshot
A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs
inferred← citeshttps://doi.org/10.1109/tifs.2018.2870835openalex-snapshot
Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response
inferred← citeshttps://doi.org/10.1109/tpds.2020.2995562openalex-snapshot
Efficient Parallelism of Post-Quantum Signature Scheme SPHINCS
inferred← citeshttps://doi.org/10.1109/trustcom/bigdatase/icess.2017.270openalex-snapshot
Secure FPGA as a Service — Towards Secure Data Processing by Physicalizing the Cloud
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2271696openalex-snapshot
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3073946openalex-snapshot
Physical Attack Protection Techniques for IC Chip Level Hardware Security
inferred← citeshttps://doi.org/10.1109/vlsi.2008.82openalex-snapshot
Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm
inferred← citeshttps://doi.org/10.1109/vlsid.2012.108openalex-snapshot
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks
inferred← citeshttps://doi.org/10.1142/s0218126614500364openalex-snapshot
PERFORMANCE CHARACTERIZATION OF PIPELINED S-BOX IMPLEMENTATIONS FOR THE ADVANCED ENCRYPTION STANDARD
inferred← citeshttps://doi.org/10.1145/1229285.1229323openalex-snapshot
Compact FPGA implementations of QUAD
inferred← citeshttps://doi.org/10.1145/1661438.1661441openalex-snapshot
DSPs, BRAMs, and a Pinch of Logic
inferred← citeshttps://doi.org/10.1145/2934677openalex-snapshot
A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities
inferred← citeshttps://doi.org/10.1145/3492735openalex-snapshot
ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata Recovery
inferred← citeshttps://doi.org/10.1145/3503823.3503882openalex-snapshot
Secure Video Transmission System for UAV Applications
inferred← citeshttps://doi.org/10.1145/3672758.3672823openalex-snapshot
Research on Implementing Encryption Algorithms on Reconfigurable Arrays
inferred← citeshttps://doi.org/10.1155/2013/696717openalex-snapshot
An 8-Bit ROM-Free AES Design for Low-Cost Applications
inferred← citeshttps://doi.org/10.11591/ijece.v11i5.pp4221-4232openalex-snapshot
High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications
inferred← citeshttps://doi.org/10.11591/ijres.v7.i3.pp151-159openalex-snapshot
High Speed Area Efficient FPGA Implementation of AES Algorithm
inferred← citeshttps://doi.org/10.11591/ijres.v7.i3.pp157-165openalex-snapshot
High Speed Area Efficient FPGA Implementation of AES Algorithm
inferred← citeshttps://doi.org/10.1186/s13634-022-00963-3openalex-snapshot
A reconfigurable and compact subpipelined architecture for AES encryption and decryption
inferred← citeshttps://doi.org/10.1186/s13638-024-02419-8openalex-snapshot
FPGA-based dual-layer authentication scheme utilizing AES and ECC for unmanned aerial vehicles
inferred← citeshttps://doi.org/10.13053/cys-12-3-1207openalex-snapshot
Hardware Architecture and Cost/time/data Trade-off for Generic Inversion of One-Way Function
inferred← citeshttps://doi.org/10.15760/etd.3651openalex-snapshot
Systematic Characterization of Power Side Channel Attacks for Residual and Added Vulnerabilities
inferred← citeshttps://doi.org/10.18280/ts.390305openalex-snapshot
Optimized Piccolo Lightweight Block Cipher: Area Efficient Implementation
inferred← citeshttps://doi.org/10.23919/fpl.2017.8056817openalex-snapshot
A security library for FPGA interlays
inferred← citeshttps://doi.org/10.2478/v10177-011-0034-7openalex-snapshot
Implementation and Analysis of Elliptic Curves-Based Cryptographic Algorithms in the Integrated Programming Environment
inferred← citeshttps://doi.org/10.2478/v10187-012-0042-6openalex-snapshot
Block–wise authentication method for digital images
inferred← citeshttps://doi.org/10.25916/sut.26294107openalex-snapshot
VLSI implementation and its optimisation for digital cryptosystems
inferred← citeshttps://doi.org/10.26083/tuprints-00001327openalex-snapshot
Efficient and Flexible Cryptographic Co-Processor Architecture for Server Application
inferred← citeshttps://doi.org/10.3182/20071107-3-fr-3907.00030openalex-snapshot
AES-CCM IMPLEMENTATIONS FOR THE IEEE 802.15.4 DEVICES
inferred← citeshttps://doi.org/10.3233/apc210288openalex-snapshot
Improving Security Using Modified S-Box for AES Cryptographic Primitives
inferred← citeshttps://doi.org/10.32657/10220/46622openalex-snapshot
Arbiter PUF based FPGA chip identification and authentication methods with enhanced reliability and modeling attack resistance
inferred← citeshttps://doi.org/10.32920/ryerson.14647833openalex-snapshot
RFID security protocols simulation and prototyping
inferred← citeshttps://doi.org/10.32920/ryerson.14647833.v1openalex-snapshot
RFID security protocols simulation and prototyping
inferred← citeshttps://doi.org/10.3390/e17063692openalex-snapshot
The Switching Generator: New Clock-Controlled Generator with Resistance against the Algebraic and Side Channel Attacks
inferred← citeshttps://doi.org/10.3390/sym18071083openalex-snapshot
Exploiting Structural Symmetry of SM4 for an Asymmetric Hardware Architecture: Design and Open-Source Verification on the RISC-V LicheePi 4A Platform
inferred← citeshttps://doi.org/10.35940/ijitee.k1088.09811s19openalex-snapshot
SAL – A Lightweight Symmetric Cipher for Internet-of-Things
inferred← citeshttps://doi.org/10.4156/jcit.vol7.issue8.27openalex-snapshot
An AES Evaluation for 2.4GHz Wireless Network Based on SOPC
inferred← citeshttps://doi.org/10.46532/978-81-950008-1-4_018openalex-snapshot
Low Power Lut Architecture To Enhance Stability
inferred← citeshttps://doi.org/10.46586/tches.v2021.i1.109-136openalex-snapshot
The design of scalar AES Instruction Set Extensions for RISC-V
inferred← citeshttps://doi.org/10.47839/ijc.14.2.803openalex-snapshot
IMPLEMENTATION OF SYMMETRIC CRYPTOGRAPHY IN EMBEDDED MEASUREMENT SYSTEMS
inferred← citeshttps://doi.org/10.5120/16097-5423openalex-snapshot
FPGA Implementation of Low Power and High Speed Hummingbird Cryptographic Algorithm
inferred← citeshttps://doi.org/10.51201/jusst/21/05162openalex-snapshot
A Dynamic and Highly Configurable Crypto-Processor for brief communication interval
inferred← citeshttps://doi.org/10.5772/intechopen.78497openalex-snapshot
Computer and Network Security
inferred← citeshttps://doi.org/10.5772/intechopen.82434openalex-snapshot
High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform
inferred← citeshttps://doi.org/10.5815/ijcnis.2015.12.07openalex-snapshot
FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95823openalex-snapshot
Generación de falsas claves criptográficas como medida de protección frente a ataques por canal lateral
inferred← citeshttps://doi.org/10.5937/vojtehg63-7392openalex-snapshot
Implementation of cryptology algorithms in high bit rate systems
inferred← citeshttps://doi.org/10.70675/2bd1f905z512bz45cbzb346z52d6489202f3openalex-snapshot
Balancing energy, security and circuit area in lightweight cryptographic hardware design
inferred← citeshttps://doi.org/10.70675/6ea09c8bz1140z4416z9afez41888dc17ac7openalex-snapshot
Authenticated Encryption on FPGAs from the Reconfigurable Part to the Static Part
inferred← citeshttps://doi.org/10.70675/71a2c7d3z62d8z41f2zb10dzc8b8a145c036openalex-snapshot
De la vulnérabilité des nœuds capteurs à la certification des transactions sur le réseau, une approche de la sécurisation de l’Internet des Objets
inferred← citeshttps://doi.org/10.7763/ijcte.2019.v11.1253openalex-snapshot
The Compatibility Analysis of AES Algorithm for Design Portability on FPGA
inferred← citeshttps://doi.org/10.7916/d8n014pxopenalex-snapshot
Producing Trustworthy Hardware Using Untrusted Components, Personnel and Resources
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.