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FPGA implementation of AES algorithm for high throughput using folded parallel architecture

https://doi.org/10.1002/sec.651
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/11545262_31openalex-snapshot
AES on FPGA from the Fastest to the Smallest
inferredcites →https://doi.org/10.1007/3-540-44709-1_6openalex-snapshot
Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
inferredcites →https://doi.org/10.1007/3-540-44709-1_8openalex-snapshot
Two Methods of Rijndael Implementation in Reconfigurable Hardware
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_59openalex-snapshot
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_29openalex-snapshot
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_26openalex-snapshot
Very Compact FPGA Implementation of the AES Algorithm
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_27openalex-snapshot
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
inferredcites →https://doi.org/10.1007/978-3-540-68164-9_2openalex-snapshot
Implementation of the AES-128 on Virtex-5 FPGAs
inferredcites →https://doi.org/10.1007/978-3-540-74735-2_15openalex-snapshot
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
inferredcites →https://doi.org/10.1007/978-3-540-74735-2_16openalex-snapshot
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
inferredcites →https://doi.org/10.1016/j.micpro.2004.12.001openalex-snapshot
An AES crypto chip using a high-speed parallel pipelined architecture
inferredcites →https://doi.org/10.1016/j.vlsi.2009.05.003openalex-snapshot
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
inferredcites →https://doi.org/10.1049/el:20030746openalex-snapshot
4.2 Gbit/s single-chip FPGA implementation of AES algorithm
inferredcites →https://doi.org/10.1109/compsac.2007.62openalex-snapshot
An Efficient Software Implementation of AES-CCM for IEEE 802.11i Wireless St
inferredcites →https://doi.org/10.1109/dsd.2004.1333297openalex-snapshot
A high speed FPGA implementation of the Rijndael algorithm
inferredcites →https://doi.org/10.1109/dsd.2004.8openalex-snapshot
A high speed FPGA implementation of the Rijndael algorithm
inferredcites →https://doi.org/10.1109/dsd.2006.40openalex-snapshot
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
inferredcites →https://doi.org/10.1109/enc.2003.1232885openalex-snapshot
AES algorithm implementation - an efficient approach for sequential and pipeline architectures
inferredcites →https://doi.org/10.1109/fccm.2004.1openalex-snapshot
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
inferredcites →https://doi.org/10.1109/icspc.2007.4728256openalex-snapshot
CUDA Compatible GPU as an Efficient Hardware Accelerator for AES Cryptography
inferredcites →https://doi.org/10.1109/iscas.2004.1329342openalex-snapshot
An efficient FPGA implementation of advanced encryption standard algorithm
inferredcites →https://doi.org/10.1109/iscas.2005.1465670openalex-snapshot
AES Crypto Chip Utilizing High-Speed Parallel Pipelined Architecture
inferredcites →https://doi.org/10.1109/itcc.2004.1286716openalex-snapshot
Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
inferredcites →https://doi.org/10.1109/mwscas.2002.1187269openalex-snapshot
A hardware implementation in FPGA of the Rijndael algorithm
inferredcites →https://doi.org/10.1109/sips.2001.957363openalex-snapshot
Rijndael FPGA implementation utilizing look-up tables
inferredcites →https://doi.org/10.1109/tc.2002.1146712openalex-snapshot
Architectures and VLSI implementations of the AES-Proposal Rijndael
inferredcites →https://doi.org/10.1109/tc.2006.49openalex-snapshot
Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors
inferredcites →https://doi.org/10.1109/tvlsi.2004.832943openalex-snapshot
High-speed VLSI architectures for the AES algorithm
inferredcites →https://doi.org/10.1145/611817.611848openalex-snapshot
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
inferredcites →https://doi.org/10.1145/611817.611849openalex-snapshot
A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL
inferredcites →https://doi.org/10.48550/arxiv.0909.2369openalex-snapshot
Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.4758openalex-snapshot
Implementation and optimization of a data protecting model on the Sunway TaihuLight supercomputer with heterogeneous many‐core processors
inferred← citeshttps://doi.org/10.1002/cpe.5257openalex-snapshot
A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration
inferred← citeshttps://doi.org/10.1002/sec.1479openalex-snapshot
Modeling and optimization of the lightweight HIGHT block cipher design with FPGA implementation
inferred← citeshttps://doi.org/10.1002/sec.1533openalex-snapshot
An FPGA-based reconfigurable IPSec AH core with efficient implementation of SHA-3 for high speed IoT applications
inferred← citeshttps://doi.org/10.1007/978-3-031-71729-1_21openalex-snapshot
Promoting Sustainable Security by Implementing AES Algorithm for Enhanced Confidentiality in UART Serial Communication
inferred← citeshttps://doi.org/10.1007/978-981-19-6383-4_4openalex-snapshot
A Survey on Performance Analysis of Different Architectures of AES Algorithm on FPGA
inferred← citeshttps://doi.org/10.1007/978-981-99-7633-1_7openalex-snapshot
Implementation of the AES Algorithm on FPGA
inferred← citeshttps://doi.org/10.1007/s10470-021-01959-zopenalex-snapshot
FPGA implementation of AES algorithm for high speed applications
inferred← citeshttps://doi.org/10.1007/s11277-016-3385-7openalex-snapshot
An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box
inferred← citeshttps://doi.org/10.1007/s11277-021-08325-2openalex-snapshot
Optimized Implementation of Gift Cipher
inferred← citeshttps://doi.org/10.1007/s13389-025-00388-2openalex-snapshot
First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES
inferred← citeshttps://doi.org/10.1007/s41870-020-00465-1openalex-snapshot
A novel method of improvement in advanced encryption standard algorithm with dynamic shift rows, sub byte and mixcolumn operations for the secure communication
inferred← citeshttps://doi.org/10.1016/j.jisa.2018.01.001openalex-snapshot
Bump in the wire (BITW) security solution for a marine ROV remote control application
inferred← citeshttps://doi.org/10.1016/j.jksuci.2016.01.004openalex-snapshot
Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA
inferred← citeshttps://doi.org/10.1016/j.mejo.2014.05.004openalex-snapshot
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.07.005openalex-snapshot
An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
inferred← citeshttps://doi.org/10.1063/5.0168006openalex-snapshot
An innovative approach for runtime analysis of 128 bits AES algorithm by comparing with DES algorithm using VHDL
inferred← citeshttps://doi.org/10.1109/aimlcps68702.2026.11542469openalex-snapshot
High-Performance AES-128 Implementation on FPGA: A Comparative Study
inferred← citeshttps://doi.org/10.1109/compcomm.2018.8780921openalex-snapshot
Optimization and Implementation of AES Algorithm Based on FPGA
inferred← citeshttps://doi.org/10.1109/ddecs.2014.6868783openalex-snapshot
High throughput architecture for the Advanced Encryption Standard Algorithm
inferred← citeshttps://doi.org/10.1109/ic_aset58101.2023.10150938openalex-snapshot
A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform
inferred← citeshttps://doi.org/10.1109/icm60448.2023.10378909openalex-snapshot
Computational-Based Advanced Encryption Standard (AES) Accelerator
inferred← citeshttps://doi.org/10.1109/icnisc.2018.00083openalex-snapshot
User Space or Kernel Space: Performance Evaluation of QAT Accelerator
inferred← citeshttps://doi.org/10.1109/icscst70031.2026.11709603openalex-snapshot
Design and Implementation of AES Encryption and Decryption Cores Supporting 128, 192, and 256-Bit Keys on Artix-7
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9181186openalex-snapshot
DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs
inferred← citeshttps://doi.org/10.1109/isncc.2017.8071975openalex-snapshot
High speed efficient advanced encryption standard implementation
inferred← citeshttps://doi.org/10.1109/radioelektronika49387.2020.9092417openalex-snapshot
Design of Efficient AES Architecture for Secure ECG Signal Transmission for Low-power IoT Applications
inferred← citeshttps://doi.org/10.1109/radioelektronika57919.2023.10109046openalex-snapshot
Comparison of Hardware Implementations of Cryptographic Algorithms for IoT Applications
inferred← citeshttps://doi.org/10.1109/socc.2016.7905466openalex-snapshot
Efficient implementation of the AES algorithm for security applications
inferred← citeshttps://doi.org/10.1142/s0218126617501419openalex-snapshot
Hardware Implementation of AES Algorithm with Logic S-box
inferred← citeshttps://doi.org/10.1142/s0218126619500622openalex-snapshot
Low-Cost AES-128 Implementation for Edge Devices in IoT Applications
inferred← citeshttps://doi.org/10.1155/2018/4804729openalex-snapshot
Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding
inferred← citeshttps://doi.org/10.11591/ijeecs.v35.i1.pp397-404openalex-snapshot
An efficient controller-based architecture for AES algorithm using FPGA
inferred← citeshttps://doi.org/10.14569/ijacsa.2017.080249openalex-snapshot
A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio
inferred← citeshttps://doi.org/10.14569/ijacsa.2022.0130183openalex-snapshot
Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA
inferred← citeshttps://doi.org/10.17762/ijcnis.v14i1.5260openalex-snapshot
A High-Throughput Hardware Implementation of NAT Traversal For IPSEC VPN
inferred← citeshttps://doi.org/10.21123/bsj.2024.8931openalex-snapshot
Design Hybrid Architecture to Implement AES Algorithm on FPGA for IoT Applications
inferred← citeshttps://doi.org/10.2174/1874110x01509012248openalex-snapshot
Performance Analysis of AES Algorithm on MPC Processor
inferred← citeshttps://doi.org/10.3390/computation7040063openalex-snapshot
Field Programmable Gate Array Applications—A Scientometric Review
inferred← citeshttps://doi.org/10.3390/electronics10162023openalex-snapshot
A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application
inferred← citeshttps://doi.org/10.3390/electronics9101665openalex-snapshot
10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform
inferred← citeshttps://doi.org/10.3390/s21248347openalex-snapshot
Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data
inferred← citeshttps://doi.org/10.36548/jtcsst.2026.2.003openalex-snapshot
Dual-Metric Detection of Synthesis-Masked Hardware Trojans in AES-256: Correlating Power Signatures with Switching Activity
inferred← citeshttps://doi.org/10.4018/978-1-7998-1763-5.ch008openalex-snapshot
Hybrid Approach of Modified AES
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Securing AES Accelerator from Key-Leaking Trojans on FPGA
inferred← citeshttps://doi.org/10.4018/ijoci.2017100105openalex-snapshot
Hybrid Approach of Modified AES
inferred← citeshttps://doi.org/10.5281/zenodo.192064openalex-snapshot
FIGURE 68. C in Immature stages of Calycopis bellera (Hewitson) and C. janeirica (Felder) (Lepidoptera, Lycaenidae, Theclinae, Eumaeini): Taxonomic significance and new evidence for detritivory
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