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Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Efficient AES Implementations on ASICs and FPGAs
inferredcites →https://doi.org/10.1007/11545262_31openalex-snapshot
AES on FPGA from the Fastest to the Smallest
inferredcites →https://doi.org/10.1007/3-540-45682-1_15openalex-snapshot
A Compact Rijndael Hardware Architecture with S-Box Optimization
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_26openalex-snapshot
Strong Authentication for RFID Systems Using the AES Algorithm
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_26openalex-snapshot
Very Compact FPGA Implementation of the AES Algorithm
inferredcites →https://doi.org/10.1049/ip-ifs:20055006openalex-snapshot
AES implementation on a grain of sand
inferredcites →https://doi.org/10.1109/icm.2004.1434230openalex-snapshot
Mapping of high-bit algorithm to low-bit for optimized hardware implementation
inferredcites →https://doi.org/10.1109/itcc.2004.1286716openalex-snapshot
Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
inferredcites →https://doi.org/10.1109/mwscas.2005.1594143openalex-snapshot
Efficient hardware implementation of security processing for IEEE 802.15.4 wireless networks
inferredcites →https://doi.org/10.5281/zenodo.39319openalex-snapshot
Efficient Byte Permutation Realizations For Compact Aes Implementations
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers
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Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security Applications
inferred← citeshttps://doi.org/10.1109/isvlsi.2015.22openalex-snapshot
SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00064openalex-snapshot
Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility
inferred← citeshttps://doi.org/10.1109/jiot.2022.3203182openalex-snapshot
A Flexible and Efficient Privacy-Preserving Range Query Scheme for Blockchain-Enhanced IoT
inferred← citeshttps://doi.org/10.1109/jiot.2023.3265683openalex-snapshot
Securing AES Designs Against Power Analysis Attacks: A Survey
inferred← citeshttps://doi.org/10.1109/jproc.2015.2399275openalex-snapshot
High-Level Language Tools for Reconfigurable Computing
inferred← citeshttps://doi.org/10.1109/jsac.2010.100908openalex-snapshot
A randomized countermeasure against parasitic adversaries in wireless sensor networks
inferred← citeshttps://doi.org/10.1109/jssc.2014.2384039openalex-snapshot
340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
inferred← citeshttps://doi.org/10.1109/jssc.2019.2915203openalex-snapshot
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications
inferred← citeshttps://doi.org/10.1109/lascas45839.2020.9069025openalex-snapshot
A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment
inferred← citeshttps://doi.org/10.1109/mdat.2016.2569433openalex-snapshot
Ultralow Power and the New Era of Not-So-VLSI
inferred← citeshttps://doi.org/10.1109/meco.2015.7181881openalex-snapshot
A compact design of SEED block cipher
inferred← citeshttps://doi.org/10.1109/micro.2018.00043openalex-snapshot
Improving the Performance and Endurance of Encrypted Non-Volatile Main Memory through Deduplicating Writes
inferred← citeshttps://doi.org/10.1109/milcom.2010.5680127openalex-snapshot
FPGA-based, multi-processor HW-SW system for Single-Chip Crypto applications
inferred← citeshttps://doi.org/10.1109/mm.2017.4241357openalex-snapshot
Hardware Designs for Security in Ultra-Low-Power IoT Systems: An Overview and Survey
inferred← citeshttps://doi.org/10.1109/mnano.2022.3141514openalex-snapshot
Efficient In-Memory AES Encryption Implementation Using a General Memristive Logic: Surmounting the data movement bottleneck
inferred← citeshttps://doi.org/10.1109/mobilecloud.2017.35openalex-snapshot
HSC-IoT: A Hardware and Software Co-Verification Based Authentication Scheme for Internet of Things
inferred← citeshttps://doi.org/10.1109/mssc.2019.2923503openalex-snapshot
Trends in Hardware Security: From Basics to ASICs
inferred← citeshttps://doi.org/10.1109/mwscas.2019.8884946openalex-snapshot
Low-Power Advanced Encryption Standard for Implantable Cardiac Devices
inferred← citeshttps://doi.org/10.1109/mwscas54063.2022.9859276openalex-snapshot
Shared Round Core Architecture: A Novel AES Implementation for Implantable Cardiac Devices
inferred← citeshttps://doi.org/10.1109/newcas.2010.5603920openalex-snapshot
Using a pipelined S-box in compact AES hardware implementations
inferred← citeshttps://doi.org/10.1109/nics.2016.7725650openalex-snapshot
An efficient FPGA implementation of AES-CCM authenticated encryption IP core
inferred← citeshttps://doi.org/10.1109/nrsc.2016.7450850openalex-snapshot
Multi-objective genetic algorithm-based optimization of an asynchronous data-flow security processor
inferred← citeshttps://doi.org/10.1109/nswctc.2009.246openalex-snapshot
An Energy-Efficient AES-CCM Implementation for IEEE802.15.4 Wireless Sensor Networks
inferred← citeshttps://doi.org/10.1109/radioelektronika57919.2023.10109046openalex-snapshot
Comparison of Hardware Implementations of Cryptographic Algorithms for IoT Applications
inferred← citeshttps://doi.org/10.1109/reconfig.2012.6416757openalex-snapshot
IPSecco: A lightweight and reconfigurable IPSec core
inferred← citeshttps://doi.org/10.1109/rfid.2011.5764619openalex-snapshot
A2U2: A stream cipher for printed electronics RFID tags
inferred← citeshttps://doi.org/10.1109/rfid.2013.6548148openalex-snapshot
On security with the new Gen2 RFID security framework
inferred← citeshttps://doi.org/10.1109/rivf68649.2025.11365140openalex-snapshot
Optimizing AES Encryption Algorithm on Resource-Constrained Devices in IoT Systems
inferred← citeshttps://doi.org/10.1109/sahcn.2008.60openalex-snapshot
GossiCrypt: Wireless Sensor Network Data Confidentiality Against Parasitic Adversaries
inferred← citeshttps://doi.org/10.1109/sbesc.2013.36openalex-snapshot
An Implementation of the AES Cipher Using HLS
inferred← citeshttps://doi.org/10.1109/silcon63976.2024.10910811openalex-snapshot
Enhancing AES Security and Performance: A Novel 8-bit Architecture with Unique Key Expansion for IoT Applications
inferred← citeshttps://doi.org/10.1109/spin57001.2023.10116674openalex-snapshot
FPGA Implementation Of a High Throughput Low Power Advanced Encryption Standard (AES-128) Cipher
inferred← citeshttps://doi.org/10.1109/tasc.2021.3075604openalex-snapshot
Logic Design and Simulation of a 128-b AES Encryption Accelerator Based on Rapid Single-Flux-Quantum Circuits
inferred← citeshttps://doi.org/10.1109/tbcas.2010.2079330openalex-snapshot
3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications
inferred← citeshttps://doi.org/10.1109/tcad.2014.2313454openalex-snapshot
Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications
inferred← citeshttps://doi.org/10.1109/tcad.2015.2398423openalex-snapshot
Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2018.2818720openalex-snapshot
Low Cost Functional Obfuscation of Reusable IP Cores Used in CE Hardware Through Robust Locking
inferred← citeshttps://doi.org/10.1109/tcad.2019.2950380openalex-snapshot
Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel
inferred← citeshttps://doi.org/10.1109/tcc.2020.3024226openalex-snapshot
Practical Multi-Keyword Ranked Search With Access Control Over Encrypted Cloud Data
inferred← citeshttps://doi.org/10.1109/tcc.2021.3131287openalex-snapshot
Efficient and Privacy-Preserving Similar Patients Query Scheme Over Outsourced Genomic Data
inferred← citeshttps://doi.org/10.1109/tdsc.2017.2647950openalex-snapshot
Secure and Efficient Initialization and Authentication Protocols for SHIELD
inferred← citeshttps://doi.org/10.1109/tifs.2018.2868162openalex-snapshot
Enabling Efficient and Geometric Range Query With Access Control Over Encrypted Spatial Data
inferred← citeshttps://doi.org/10.1109/trustcom.2011.100openalex-snapshot
Flogger: A File-Centric Logger for Monitoring File Access and Transfers within Cloud Computing Environments
inferred← citeshttps://doi.org/10.1109/trustcom.2011.101openalex-snapshot
Remedying the Hummingbird Cryptographic Algorithm
inferred← citeshttps://doi.org/10.1109/trustcom/bigdatase.2018.00204openalex-snapshot
A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS
inferred← citeshttps://doi.org/10.1109/tsc.2021.3130633openalex-snapshot
Privacy-Preserving Top-k Spatial Keyword Queries in Fog-Based Cloud Computing
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