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A co-synthesis approach to embedded system design automation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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An Efficient Heuristic Procedure for Partitioning Graphs
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Co-Synthesis of Hardware and Software for Digital Embedded Systems
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Hardware-Software Co-Design of Embedded Systems
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High Level Synthesis of ASICs under Timing and Synchronization Constraints
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Synchronous Programming of Reactive Systems
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Predicting program execution times by analyzing static and dynamic program paths
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Synchronous programming of reactive systems
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Direct determination of traces of Ag, Cd, Pb, Bi, Cr, Mn, Co, Ni, Li, Be, Cu and Sb in environmental waters and geological materials by simultaneous multi-element graphite furnace atomic absorption spectrometry with Zeeman-effect background correction
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A framework for hardware/software codesign
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Experiments with a program timing tool based on source-level timing schema
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Reasoning about time in higher-level language software
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Hardware-software codesign of embedded systems
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Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits
inferredcites →https://doi.org/10.1109/5.293155openalex-snapshot
Hardware-software co-design of embedded systems
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A model and methodology for hardware-software codesign
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A hardware-software codesign methodology for DSP applications
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Hardware-software cosynthesis for microcontrollers
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Specification partitioning for system design
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Interactive system-level partitioning with PARTIF
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Constrained software generation for hardware-software systems
inferredcites →https://doi.org/10.1109/hsc.1994.336725openalex-snapshot
Configuration-level hardware/software partitioning for real-time embedded systems
inferredcites →https://doi.org/10.1109/iccad.1990.129884openalex-snapshot
Partitioning of functional models of synchronous digital systems
inferredcites →https://doi.org/10.1109/iccad.1992.279323openalex-snapshot
A partitioning algorithm for system-level synthesis
inferredcites →https://doi.org/10.1109/iccad.1993.580157openalex-snapshot
Sizing and verification of communication buffers for communicating processes
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The future of embedded system design
inferredcites →https://doi.org/10.1109/iccd.1993.393335openalex-snapshot
Fast timing analysis for hardware-software co-synthesis
inferredcites →https://doi.org/10.1109/real.1990.128731openalex-snapshot
Experiments with a program timing tool based on source-level timing schema
inferredcites →https://doi.org/10.1109/tse.1985.231845openalex-snapshot
Timing Constraints of Real-Time Systems: Constructs for Expressing Them, Methods of Validating Them
inferredcites →https://doi.org/10.1145/182.358434openalex-snapshot
Maintaining knowledge about temporal intervals
inferredcites →https://doi.org/10.1145/196244.196247openalex-snapshot
Software scheduling in the co-synthesis of reactive real-time systems
inferredcites →https://doi.org/10.1145/293625.293631openalex-snapshot
Rate analysis for embedded systems
inferredcites →https://doi.org/10.5555/113938.149411openalex-snapshot
Specification partitioning for system design
inferredcites →https://doi.org/10.5555/259794.259898openalex-snapshot
Sizing and verification of communication buffers for communicating processes
inferredcites →https://doi.org/10.5555/304032.304157openalex-snapshot
A partitioning algorithm for system-level synthesis
inferredcites →https://doi.org/10.5555/947185.947192openalex-snapshot
Configuration-level hardware/software partitioning for real-time embedded systems
inferredcites →https://doi.org/10.5555/947185.947195openalex-snapshot
Constrained software generation for hardware-software systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware/Software Co-Design: Application Domains and Design Technologies
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Specification and analysis of timing constraints for embedded systems
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An Efficient Implementation Of Reactivity For Modeling Hardware In The Scenic Design Environment
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Scheduling of conditional process graphs for the synthesis of embedded systems
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A model for system-level timed analysis and profiling
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Combining software synthesis and hardware/software interface generation to meet hard real-time constraints
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Operation serializability for embedded systems
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Process scheduling for performance estimation and synthesis of hardware/software systems
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An improved scheduling technique for time-triggered embedded systems
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Scheduling with optimized communication for time-triggered embedded systems
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Combining software synthesis and hardware/software interface generation to meet hard real-time constraints
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