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Experiments with a program timing tool based on source-level timing schema
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Outgoing claims: the papers this work cites, builds on, or argues with.
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WCET analysis and optimization for multi-core real-time systems
inferred← citeshttps://doi.org/10.22028/d291-25778openalex-snapshot
Control flow graphs for real-time systems analysis: reconstruction from binary executables and usage in ILP-based path analysis
inferred← citeshttps://doi.org/10.25916/sut.26283199openalex-snapshot
Hard real-time motion planning for autonomous vehicles
inferred← citeshttps://doi.org/10.3233/emc-2005-00014openalex-snapshot
Probabilistic timing analysis: An approach using copulas
inferred← citeshttps://doi.org/10.32657/10356/41131openalex-snapshot
Methods for rapid selection of processors for constraint-aware embedded systems
inferred← citeshttps://doi.org/10.3745/kipsta.2005.12a.5.365openalex-snapshot
Implementation of Worst Case Execution Time Analysis Tool For Embedded Software based on XScale Processor
inferred← citeshttps://doi.org/10.4230/oasics.wcet.2006.675openalex-snapshot
Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis
inferred← citeshttps://doi.org/10.4271/2005-01-1290openalex-snapshot
Standard Software Modules - One Key for Future Distributed Systems
inferred← citeshttps://doi.org/10.4995/thesis/10251/55328openalex-snapshot
Utilización de memorias cache con bloqueo en sistemas de tiempo real.
inferred← citeshttps://doi.org/10.5555/501790.501819openalex-snapshot
Intervals in software execution cost analysis
inferred← citeshttps://doi.org/10.5555/947185.947195openalex-snapshot
Constrained software generation for hardware-software systems
inferred← citeshttps://doi.org/10.5555/947185.947220openalex-snapshot
A case study in computer-aided codesign of embedded controllers
inferred← citeshttps://doi.org/10.6688/jise.2006.22.5.14openalex-snapshot
Bounding DMA Interference on Hard-Real-Time Embedded Systems *
inferred← citeshttps://doi.org/10.67635/pjeas.2021.29.1.302openalex-snapshot
An investigation of characteristics of Materials and Techniques used for the repair of Kala Burj, Lahore Fort, Lahore
inferred← citeshttps://doi.org/10.70675/29c4dcbaz365ez4589zad7ez2e35c1b7665copenalex-snapshot
Maîtrise du temps d'exécution de logiciels déployés dans des dispositifs personnels de confiance
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Calcul du pire temps d'exécution : méthode formelle s'adaptant à la sophistication croissante des architectures matérielles
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